Through-Silicon Via Structure With Glass Plug and Copper Ring
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Solution Overview
Problem
Existing technologies for forming through silicon vias face challenges in achieving low resistance and high density connections while managing thermal expansion mismatch and fabrication complexity, particularly at cryogenic temperatures, where silicon's conductivity is inadequate and copper filling techniques are difficult due to thermal expansion issues.
Innovation Solution
The use of a glass plug combined with a copper ring, where the through silicon via is etched to greater depths and lined with vapor grown glass, followed by chemomechanical polishing, to create a thermally more acceptable solution, allowing for low resistance and high density connections, and enabling the fabrication of moderate to low temperature devices with hermetically sealed parts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solid metal posts are used to achieve low resistance connections, then electrical conductivity is improved, but thermal expansion mismatch between metal and silicon wafer increases
Solution Approach 1:
The patent uses a composite structure consisting of a glass plug filled with copper. The glass material has a thermal expansion coefficient that matches silicon (approximately 2.6-3.0 ppm/K), while the copper filling provides low electrical resistance. This composite approach allows the via to exhibit both low electrical resistance and minimal thermal expansion mismatch with the silicon substrate.
2Reliability
If copper filling is used to achieve low resistance connections, then electrical conductivity is improved, but fabrication complexity increases due to thermal expansion issues
Solution Approach 1:
The via structure is segmented into two distinct functional parts: a glass plug portion that handles thermal expansion compatibility and structural support, and a copper filling portion that provides electrical conductivity. This segmentation allows each material to be optimized for its specific function while simplifying the overall fabrication process by clearly defining the roles of each material.
Solution Approach 2:
The glass plug acts as an intermediary material between the silicon substrate and the copper filling. It provides a thermal expansion buffer that protects the silicon from stress caused by copper's high thermal expansion coefficient, while still allowing the copper to be effectively deposited and connected to the silicon contacts.
3Reliability
If through silicon vias are etched to greater depths, then connection density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies precise parameter ranges for the via etching process, including via diameter (20-50 micrometers) and depth (greater than 100 micrometers). By defining these parameters within specific ranges, the process achieves high connection density while maintaining manufacturability. The glass plug formation process also benefits from parameter control, with deposition thickness specified as 5-20 micrometers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a flat silicon wafer with patterned electrical metal-lined vias, providing high conductivity and stress remediation, enabling the use of thicker wafers and facilitating the integration of both top and bottom surfaces for device fabrication, while avoiding wire bonds and improving lithography and fabrication capabilities.
Implementation Method 1
lined with greater ease. The lined hole can then be filled with a lower expansion coefficient vapor grown glass
Implementation Method 2
copper could have milliohm resistance levels... providing high conductivity and stress remediation
Implementation Method 3
The lined hole can then be filled with a lower expansion coefficient vapor grown glass. The combined structure can then be chemomechanically polished (CMP), which results in a very flat silicon wafer
Implementation Method 4
Solid metal posts provide the lowest resistance per volume, but they are likely to have the highest contrast in thermal expansion mis-match between the metal and the silicon wafer or substrate... a thermally more acceptable solution
Data Source
AI summary
One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer.