Through-Substrate Metal Interconnect Layout for Tighter Pitch Vias
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Solution Overview
Problem
There is a need for alternative methods and devices that provide back side conductive interconnect locations for semiconductor devices to increase density without the limitations of existing via-last processes.
Innovation Solution
The formation of metal-filled vias during semiconductor fabrication, subsequent to transistor formation and prior to metal routing layers, allows for tighter pitch via formation and lower resistance, integrating metal interconnects into the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If via-last process is used to form back side conductive interconnects, then device density can be increased, but manufacturing complexity and process limitations increase
Solution Approach 1:
The patent applies preliminary action by forming the conductive vias through the substrate before completing the transistor fabrication process. This allows the via formation to be integrated into the existing fabrication sequence rather than requiring a separate via-last process step, thereby reducing manufacturing complexity while maintaining the ability to achieve high device density through back side interconnects
2Reliability
If metal-filled vias are formed after transistor formation, then via resistance decreases, but process integration difficulty increases
Solution Approach 1:
The patent merges the via formation process with the transistor fabrication process by integrating metal deposition and via formation steps into the existing fabrication sequence. This combination allows for lower resistance metal-filled vias to be created without requiring separate complex process steps, as the metal deposition is coordinated with the transistor formation timeline
3Quantity of substance
If tighter pitch via formation is implemented, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by utilizing metal-filled vias which allow for tighter pitch formation. The metal filling process enables precise control of via dimensions and positioning, achieving the required manufacturing precision for tighter pitch while maintaining manufacturability through the integrated fabrication process
Data Source
AI summary
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.