Through-Substrate Via Structure for Uniform Hybrid Bonding
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Solution Overview
Problem
Conventional methods for forming through-substrate vias (TSVs) in semiconductor elements face challenges such as non-uniform etch depths, die thickness variations, and TSV breakage during polishing, leading to reduced yield and difficulty in achieving uniform surface bonding, especially in high volume manufacturing.
Innovation Solution
The method involves depositing dielectric barrier layers over the backside of semiconductor portions to stabilize copper TSVs, using selective copper wet etching and chemical-mechanical polishing (CMP) to uniformize TSV lengths, and applying annealing processes to stabilize copper plugs for direct bonding, ensuring uniformity and planarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form TSVs, then through-substrate vias can be created, but non-uniform etch depths and die thickness variations occur leading to reduced yield
Solution Approach 1:
The method performs preliminary actions by depositing dielectric barrier layers over the backside of semiconductor portions before final TSV formation, and uses selective copper wet etching to uniformly expose TSVs. Chemical-mechanical polishing (CMP) is then applied to uniformize TSV lengths before subsequent processing, preventing the non-uniformity problems that would otherwise reduce yield
Solution Approach 2:
The invention changes physical and chemical parameters through the use of dielectric barrier layers with specific dielectric properties, controlled etching parameters in selective copper wet etching, and regulated CMP process parameters. These parameter changes enable uniform TSV exposure and length uniformity across the substrate, directly addressing the etch depth uniformity issue
2Shape
If polishing is used to planarize the substrate, then surface flatness is improved, but TSV breakage occurs during the process
Solution Approach 1:
Dielectric barrier layers are deposited beforehand over the backside of semiconductor portions containing TSVs. These barrier layers act as a protective cushion during polishing, distributing mechanical stresses and preventing direct contact between the polishing medium and TSVs, thereby avoiding TSV breakage while still achieving surface planarity
Solution Approach 2:
The dielectric barrier layers serve as an intermediary protective layer between the TSVs and the polishing process. This intermediary structure allows the substrate surface to be planarized without transmitting damaging mechanical forces to the TSVs, resolving the contradiction between achieving flatness and maintaining TSV integrity
3Reliability
If uniform TSV lengths are achieved through multiple processing steps, then direct hybrid bonding becomes feasible, but process complexity increases
Solution Approach 1:
The dielectric barrier layers perform multiple functions: they protect TSVs during polishing, provide a planar surface for subsequent processing, and enable uniform TSV exposure. This multi-functionality reduces the need for separate protective structures and simplifies the overall process compared to what would be required without this universal element
Solution Approach 2:
The selective copper wet etching process automatically uniformizes TSV lengths by selectively removing material based on the barrier layer pattern, without requiring additional alignment or measurement steps. The process self-adjusts to achieve uniformity, reducing complexity compared to manual or multi-step controlled processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device yield by ensuring uniform TSV lengths and planarity, facilitating direct hybrid bonding without adhesives, suitable for high volume manufacturing.
Implementation Method 1
selective copper wet etching to uniformize TSV lengths
Implementation Method 2
chemical-mechanical polishing (CMP) to uniformize TSV lengths
Implementation Method 3
applying annealing processes to stabilize copper plugs for direct bonding
Data Source
AI summary
A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.