Semiconductor Pattern Stack Layout for Compact Thyristor DRAM Cells
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Solution Overview
Problem
Current semiconductor technologies face challenges in maintaining desired electrical characteristics while minimizing the size of semiconductor patterns in stack structures, which is crucial for highly integrated devices.
Innovation Solution
The semiconductor device incorporates a stack structure with a first and second conductive line, where a semiconductor pattern with different conductivity types is placed between them, and a third semiconductor pattern with intrinsic layers is used, allowing for a high level of integration and excellent electrical characteristics by utilizing a specific arrangement of gate lines and conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of semiconductor patterns is minimized to achieve high integration, then the level of integration is improved, but the electrical characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating different conductivity types in different regions of the semiconductor pattern. Specifically, first-conductivity-type impurities are introduced in regions adjacent to conductive lines, while second-conductivity-type impurities are introduced in other regions, allowing each local area to have optimized electrical properties for its specific function while maintaining overall small pattern size
Solution Approach 2:
The semiconductor pattern is segmented into multiple regions with different conductivity types and impurity concentrations. The pattern includes first, second, and third semiconductor patterns with distinct impurity characteristics, allowing independent optimization of electrical properties in each segment while maintaining compact overall structure
2Reliability
If different conductivity types are used in adjacent regions, then the electrical characteristics are improved, but the device complexity increases
Solution Approach 1:
The patent merges multiple functions into a single integrated semiconductor pattern structure. The first and second conductive lines, along with the multi-region semiconductor pattern, are combined to form a compact stack structure that achieves complex electrical functionality (different conductivity types, multiple gate control) within a minimized footprint, reducing overall device complexity despite the sophisticated internal structure
Data Source
AI summary
A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.