Thyristor Layer Doping Structure for Lower Gate Sensitivity
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Solution Overview
Problem
Conventional thyristors used in protection circuits for preventing inrush current in LED lights can experience abnormal operations or malfunctions due to high gate sensitivity, which is exacerbated by minute noise.
Innovation Solution
A thyristor design with a specific semiconductor layer structure, including a third P-type semiconductor layer with higher impurity concentration connected to the gate electrode and a fourth P-type semiconductor layer with higher impurity concentration beneath the cathode electrode, separated by a second P-type semiconductor layer, to desensitize gate sensitivity and enhance dv/dt resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional thyristor structure is used with highly reliable passivation, then reliability is improved, but gate sensitivity increases causing abnormal operations
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations within the semiconductor layers. Specifically, the second P-type semiconductor layer has a lower impurity concentration than the first and third P-type semiconductor layers, while the second N-type semiconductor layer has a higher impurity concentration than the first N-type semiconductor layer. This localized variation in material properties allows the device to maintain high reliability through improved passivation while reducing gate sensitivity by creating regions that are less responsive to gate voltage variations.
Solution Approach 2:
The patent employs parameter changes by systematically varying the impurity concentrations across different semiconductor layers. The first P-type layer has impurity concentration of 1×10^16 to 1×10^18 atoms/cm³, the second P-type layer has 1×10^14 to 1×10^16 atoms/cm³, the first N-type layer has 1×10^16 to 1×10^18 atoms/cm³, and the second N-type layer has 1×10^18 to 1×10^20 atoms/cm³. These parameter changes create a profile that reduces gate sensitivity while maintaining device reliability.
2Reliability
If gate sensitivity is reduced to prevent abnormal operations, then reliability is improved, but dv/dt resistance may be affected
Solution Approach 1:
The patent uses local quality by creating specific regions with tailored impurity concentrations. The second P-type semiconductor layer with lower impurity concentration (1×10^14 to 1×10^16 atoms/cm³) acts as a buffer region that reduces gate sensitivity, while the second N-type semiconductor layer with higher impurity concentration (1×10^18 to 1×10^20 atoms/cm³) maintains adequate dv/dt resistance by providing strong carrier generation capability in the breakdown region.
Solution Approach 2:
The patent applies segmentation by dividing the semiconductor structure into distinct functional regions with different impurity concentrations. The structure is segmented into five layers (first P-type, first N-type, second P-type, second N-type, third P-type) where each layer serves a specific function. This segmentation allows independent optimization of gate sensitivity (reduced in the second P-type layer) and dv/dt resistance (maintained in the second N-type layer).
Data Source
AI summary
There is provided a thyristor with desensitized gate sensitivity. In accordance with this, the third P-type semiconductor layer, which is connected to a gate electrode, has an impurity concentration higher than that of a second P-type semiconductor layer. A fourth P-type semiconductor layer, which is in contact with each of the second P-type semiconductor layer and the second N-type semiconductor layer, is disposed below the cathode electrode, and has an impurity concentration higher than that of the second P-type semiconductor layer.