Thyristor Memory Cells with Vertical Stacking for 4F2 Density
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Solution Overview
Problem
Conventional thyristor-based memory cells face limitations in scalability, density, and integration due to difficulties in controlling thyristor dimensions, reproducing doped regions, and connecting word lines, leading to serial resistance and device failure.
Innovation Solution
The development of memory cells with vertically superposed, alternately doped regions on a conductive strap and a control gate, allowing for improved scalability and integration by using a material transfer process to form doped regions and simplify integration with logic devices, resulting in a 4F2 cell size and reduced area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional SRAM cells are used, then low voltage operation and high speed performance are achieved, but large cell area is consumed
Solution Approach 1:
The patent transitions from planar SRAM cell layout to a vertical thyristor structure where the p-n-p-n layers are stacked in the vertical dimension. This dimensional change allows the memory cell to achieve higher density by utilizing the vertical space above the substrate, reducing the horizontal footprint of each cell while maintaining functionality.
Solution Approach 2:
The invention changes the fundamental operating parameters by using a thyristor-based structure instead of transistor-based SRAM. The thyristor's unique latching behavior and lower voltage requirements enable operation at reduced voltage levels (improving energy efficiency) while achieving smaller cell area through the vertical stacking of doped regions.
2Quantity of substance
If thyristor dimensions are reduced for higher density, then memory density improves, but difficulty in controlling thyristor dimensions and reproducing doped regions increases
Solution Approach 1:
The patent employs preliminary doping actions during the formation of the vertical thyristor structure, where doped regions are created in specific vertical zones before final device assembly. This preliminary action allows precise control over dopant placement and concentration profiles, ensuring reproducible thyristor characteristics even at reduced dimensions.
Solution Approach 2:
The invention replaces traditional mechanical lithographic patterning with a material transfer process that uses bonded wafer separation to define thyristor dimensions. This substitution of the patterning mechanism enables more precise dimensional control and better reproduction of doped regions by relying on material properties rather than mechanical alignment.
3Ease of operation
If word lines are connected in conventional T-RAM cells, then cell access is enabled, but serial resistance increases and device failure occurs
Solution Approach 1:
The patent extracts the problematic word line connection architecture from conventional T-RAM cells and replaces it with a vertical thyristor structure where access is achieved through vertical current flow rather than horizontal word line scanning. This extraction eliminates the serial resistance pathway and associated reliability issues while maintaining cell access functionality.
Solution Approach 2:
The invention changes the dimension of current flow from horizontal (through word lines) to vertical (through stacked thyristor layers). This dimensional change in the access path eliminates serial resistance accumulation and improves device reliability while enabling efficient cell access through the vertical transport of charge carriers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances scalability, density, and integration capacity of memory cells, enabling their integration with logic devices and reducing serial resistance, thus improving the performance and reliability of memory devices.
Implementation Method 1
A thyristor in a memory device may be turned on by biasing the gate so that a p-n-p-n channel conducts a current. Once the device is turned on, often referred to as 'latched,' the thyristor does not require the gate to be biased to maintain the current conducted between the cathode and the anode.
Implementation Method 2
The development of memory cells with vertically superposed, alternately doped regions on a conductive strap and a control gate, allowing for improved scalability and integration by using a material transfer process to form doped regions
Data Source
AI summary
Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.