Tiled Display PCB Layout With Parallel Traces for Low Power Drop
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Solution Overview
Problem
Large-scale displays face challenges such as high costs due to expensive IC chips and power drops, especially in environmentally friendly designs, necessitating a solution that retains minimal power loss while maintaining budget constraints.
Innovation Solution
The electronic device comprises a first substrate with patterned traces and unit tiles, where electrical components are connected via suppletory traces in parallel with the first patterned trace, reducing equivalent resistance and impedance, and includes conductive structures through holes in the tiles for efficient power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If large-scale display size is expanded, then display area is increased, but power drop increases
Solution Approach 1:
The display device is divided into multiple unit tiles, each with its own driving board and suppletory traces. This segmentation allows each tile to be independently driven with sufficient current, preventing power drop across the entire large-scale display while maintaining a large total display area.
2Ease of manufacture
If conventional IC chips and photomasks are used, then manufacturing process is established, but fabrication cost increases
Solution Approach 1:
The patent replaces expensive conventional IC chips and photomasks with cost-effective suppletory traces formed through printed circuit board fabrication processes. This substitution significantly reduces material costs while maintaining functional equivalence for driving the display tiles.
Solution Approach 2:
The patent replaces complex photomask-based semiconductor fabrication with simpler printed circuit board manufacturing techniques for creating the driving patterns. This substitution reduces both equipment requirements and fabrication costs while achieving the same functional outcome.
3Reliability
If suppletory traces are added in parallel, then equivalent resistance is reduced, but device complexity increases
Solution Approach 1:
The suppletory traces are merged with the existing patterned traces on the first substrate to form a parallel circuit configuration. This integration approach reduces equivalent resistance without requiring completely separate trace systems, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes power loss and enables cost-effective, efficient fabrication of large-scale displays with advanced technology, balancing flexibility and convention for diverse display applications.
Implementation Method 1
an equivalent resistance from the electrical parallel connection between the one or more suppletory traces and corresponding ones of the first patterned trace of the first substrate is formed to be less than an impedance of the first patterned trace
Data Source
AI summary
An electronic device includes a first substrate, multiple unit tiles, multiple electrical components, multiple holes, and multiple conductors. The first substrate includes a first patterned trace, multiple driving members electrically connected with the first patterned trace, and multiple pads electrically connected with the first patterned trace and respectively corresponding with the driving members. Each of the unit tiles defines a second face and a first face opposing to each other, the electrical components are disposed on the second faces of the unit tiles, and the conductors are exposed from the first faces of the unit tiles and respectively corresponding with the electrical components. The conductors are arranged in the holes respectively and overlapping the pads of the first substrate respectively for electrically connecting the electrical components to the pads of the first substrate, wherein the conductors are underneath the second faces of the unit tiles.