Tiler Pipeline Parallel Processing for Graphics Throughput

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Solution Overview

Problem

Existing tile-based graphics processing systems face inefficiencies in preparing tile-lists, leading to processing bottlenecks and reduced throughput due to strict serialization of draw calls, which can stall vertex data fetching and limit graphics processing performance.

Innovation Solution

The proposed solution relaxes ordering constraints within the tiler pipeline, allowing draw calls to be processed out of order in early stages while enforcing the desired ordering only at the final stage, using a re-order buffer or parallel processing to generate tile-lists that maintain correct rendering order, thereby improving resource utilization and throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If draw calls are processed in strict serial order in the tiler pipeline, then rendering order is maintained, but processing throughput is reduced and stalling occurs

Engineering Contradiction:
Improverendering order correctnessVSAvoidprocessing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the tiler pipeline into multiple independent processing stages (e.g., stage 520, 522, 524, 526) that can operate in parallel on different draw calls. Each stage processes specific aspects of draw calls independently, allowing simultaneous processing of multiple draw calls across stages while maintaining correct rendering order through controlled output assembly.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate buffers and control mechanisms between processing stages to mediate the parallel processing flow. These intermediaries hold and reorder draw call data to ensure that despite parallel processing, the final output maintains the correct rendering sequence, resolving the contradiction between parallelism and order preservation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If vertex data fetching is strictly serialized, then processing simplicity is maintained, but performance is limited due to bottlenecks

Engineering Contradiction:
Improvepipeline complexityVSAvoidgraphics processing performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The vertex data fetching process is divided into multiple parallel fetching operations across different pipeline stages. Instead of a single serialized fetch operation, multiple stages simultaneously fetch vertex data for different draw calls, reducing bottlenecks while maintaining manageable complexity through modular stage design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary vertex data fetching in early pipeline stages before rendering is complete. Vertex data is fetched and prepared in advance during intermediate processing stages, allowing subsequent stages to proceed without waiting for data, thereby improving performance without significantly increasing overall system complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11361485B2Graphics processing
Publication Date: 2022.06.14 ARM LTD
  • US11361485B2 patent drawing
  • US11361485B2 patent drawing
  • US11361485B2 patent drawing

AI summary

When generating a set of tile-lists for use in a tile-based graphics processing system when rendering a scene for display, vertex data is obtained for a plurality of draw calls, and the obtained vertex data is then processed to generate for each of the draw calls data indicative of which tile(s) the primitives associated with that draw call should be rendered for when rendering the scene for display. The vertex data for at least some of the plurality of draw calls can be obtained and processed out of order and/or in parallel and the data is then sorted based on a desired rendering order for the draw calls in order to generating a tile-list identifying the sequence of draw calls to be rendered. In embodiments, the generated data is sorted using a re-ordering buffer.