Tilted Plasma Etching Overlay Compensation for IC Pattern Alignment
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Solution Overview
Problem
The challenge in integrated circuit (IC) design is the non-uniform etch rate during plasma etching, which leads to overlay measurement errors between circuit patterns of upper and lower layers due to the divergence of plasma beams, causing inconsistencies in the fabrication of precise shapes on the substrate.
Innovation Solution
The implementation of a tilted angle plasma etching process, where the plasma beam is angled to induce a controlled divergence, and an etch control circuit adjusts the flow rate of etching gases to maintain uniformity, coupled with a film thickness measurement system to determine and compensate for etch rate variations, ensuring precise pattern alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If plasma beam is used for etching, then etching capability is improved, but etch rate uniformity deteriorates due to beam divergence
Solution Approach 1:
The patent applies parameter changes by adjusting the flow rate of etching gases (such as SF6, CF4, or C4F8) dynamically during the plasma etching process. By modifying gas flow parameters, the system compensates for etch rate variations caused by plasma beam divergence, thereby maintaining uniform etching across different regions of the substrate while preserving the etching capability provided by the plasma beam.
Solution Approach 2:
The patent implements feedback control through an etch control circuit that receives real-time data on etch rates from different regions of the substrate. This feedback mechanism allows the system to detect etch rate non-uniformity and automatically adjust etching parameters (such as gas flow rates or plasma power) to compensate for deviations, ensuring consistent etching performance across the entire substrate area.
2Shape
If tilted angle plasma etching is applied, then shape control is improved, but overlay measurement accuracy deteriorates due to non-uniform etching
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting etching gas flow rates during tilted angle plasma etching. This allows the system to compensate for the non-uniform etching inherent in tilted angle processes, maintaining consistent etch rates across different regions. By doing so, the patent preserves the shape control advantages of tilted angle etching while eliminating the overlay measurement errors that would otherwise result from etch rate non-uniformity.
3Manufacturing precision
If overlay offset compensation is implemented, then pattern alignment is improved, but process complexity increases
Solution Approach 1:
The patent implements feedback control through an integrated etch control circuit that automatically measures etch rates from different substrate regions and adjusts etching parameters in real-time. This automated feedback mechanism achieves overlay offset compensation and improves pattern alignment without requiring complex manual intervention or additional processing steps, thereby managing process complexity while enhancing manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overlay offset errors by compensating for non-uniform etching, achieving precise alignment and uniformity in circuit patterns across the substrate, thereby enhancing the accuracy and reliability of IC fabrication.
Implementation Method 1
The geometric shapes may be produced by plasma etching, e.g., by plasma etching with a plasma beam, of a top layer on the substrate
Implementation Method 2
the shapes may be fine-tuned by tilted angle plasma etching
Data Source
AI summary
In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.