Time-Interleaved Frequency Divider Using Parallel CMOS Counters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-frequency frequency dividers based on flip-flop circuitry face challenges with power efficiency, as high-speed components like CML circuits consume static bias current, making them inefficient, especially when handling input signals above 2 GHz.
Innovation Solution
A multi-modulus frequency divider and event counter design utilizing time-interleaved multi-clock generators, bit counters, multiplexers, and a multiplexer selection module, which generates time-interleaved clock signals and distributes events across multiple counters to reduce the frequency and power requirements, allowing for the use of CMOS logic for improved efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CML circuits are used for high-speed frequency division above 2 GHz, then transition speed is improved, but power consumption increases due to static bias current
Solution Approach 1:
The frequency division function is segmented into multiple parallel counters operating at lower frequencies. Instead of using a single high-speed CML counter, the system divides the counting task across multiple CMOS counters, each handling a portion of the frequency division. This segmentation allows the use of power-efficient CMOS logic while maintaining the required overall counting speed through parallel operation.
Solution Approach 2:
The system employs periodic clock signals to alternately enable different groups of counters. By using periodic enable signals, the counters are activated in alternating phases, allowing each counter to operate at a lower frequency than the input signal. This periodic action reduces the speed requirement for individual counters, enabling the use of CMOS instead of CML and thereby reducing power consumption.
2Device complexity
If a single high-speed counter is used, then device complexity is reduced, but power efficiency deteriorates
Solution Approach 1:
The counting function is segmented across multiple parallel counters instead of using a single counter. This segmentation increases the number of circuit elements but reduces the speed requirement for each individual counter, enabling the use of power-efficient CMOS logic. The overall system achieves the required performance through parallel operation while maintaining power efficiency.
Solution Approach 2:
Multiple counter outputs are merged through a combination logic circuit to produce the final frequency-divided output. The individual counter results are combined using logical operations to achieve the desired division ratio. This merging approach allows the system to use multiple low-power CMOS counters instead of a single high-power CML counter.
3Use of energy by moving object
If CMOS logic is used for power efficiency, then power consumption is reduced, but maximum operating frequency decreases
Solution Approach 1:
The frequency division task is segmented into multiple parallel counting operations, each running at a lower frequency that CMOS logic can handle efficiently. By dividing the overall counting requirement across multiple slower counters operating in parallel, the system achieves high-frequency division capability using power-efficient CMOS logic without requiring any single counter to operate beyond CMOS speed limits.
Solution Approach 2:
The system uses periodic enable signals to alternately activate different counter groups, effectively multiplying the operating frequency by the number of alternating phases. Each counter operates at a lower frequency determined by CMOS capabilities, but the periodic switching between multiple counters achieves an effective system frequency that exceeds what a single CMOS counter could handle.
Data Source
AI summary
Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.