Time-Mode Arithmetic Unit With RC Weighting for PVT-Robust ADPLLs
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Solution Overview
Problem
Current time-mode circuits face challenges in performing weighted operations on time-mode signals due to sensitivity to Process Voltage Temperature (PVT) variations and complexity in implementation, particularly in adapting to dynamic range requirements and high-resolution time-to-digital conversion.
Innovation Solution
A Time-mode Arithmetic Unit (TAU) circuit arrangement that varies the discharge rate of a capacitive circuit element based on control signals, enabling weighted operations by tuning the RC time constant, allowing for adaptable and low-complexity implementation in All-Digital Phase-Locked Loops (ADPLLs) with reduced PVT sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional time-mode circuits are used to perform weighted operations, then the operations can be performed on time-mode signals, but the circuits exhibit high sensitivity to PVT variations and require complex implementation
Solution Approach 1:
The patent replaces conventional voltage-mode or current-mode arithmetic circuits with a time-mode circuit that uses capacitor discharge timing to perform weighted operations. The mechanical/electrical system of traditional analog arithmetic is substituted with a time-based system where the discharge time of a capacitor through a resistor directly encodes the arithmetic result, simplifying the circuit structure and reducing PVT sensitivity.
Solution Approach 2:
The patent changes the operating parameter from voltage or current levels to time duration. By measuring the time it takes for a capacitor to discharge to a threshold voltage, the circuit performs weighted operations where the weight is encoded in the RC time constant. This parameter transformation makes the circuit less sensitive to PVT variations because time measurements are more stable than voltage or current measurements in analog circuits.
2Adaptability or versatility
If the discharge rate of the capacitive circuit element is varied to enable weighted operations, then adaptability is improved, but the control complexity increases
Solution Approach 1:
The patent introduces dynamic control of the discharge rate by allowing the RC time constant to be adjusted based on control signals. The resistor or capacitor value can be changed dynamically to implement different weights in the arithmetic operation. This dynamic capability enables the same physical circuit to perform multiple different weighted operations without requiring separate dedicated circuits for each operation.
Solution Approach 2:
The patent creates a universal time-mode arithmetic unit that can perform various weighted operations (addition, subtraction, multiplication by constants) using a single capacitor discharge mechanism. By controlling the discharge rate through adjustable RC time constants, one circuit implementation serves multiple arithmetic functions, improving adaptability while maintaining relatively simple circuit structure.
3Measurement precision
If conventional circuits are used for high-resolution time-to-digital conversion, then measurement precision is improved, but the system complexity and calibration requirements increase
Solution Approach 1:
The patent employs a self-calibrating mechanism where the circuit automatically compensates for PVT variations through its intrinsic operation. The time-mode arithmetic unit and time-to-digital converter are designed to self-adjust by using the actual discharge timing characteristics under current process, voltage, and temperature conditions, eliminating the need for external calibration procedures or complex calibration circuits.
Solution Approach 2:
The patent incorporates feedback mechanisms in the time-to-digital conversion process where the measured time values are used to adjust subsequent measurements or operations. This feedback allows the system to maintain high measurement precision by compensating for drift and variations in real-time, reducing the need for complex periodic calibration while maintaining high resolution time measurements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The TAU circuit arrangement facilitates efficient weighted operations and time-mode signal processing with improved PVT robustness and reduced system complexity, enabling effective time amplification and summation while minimizing the need for complex calibration and power consumption.
Implementation Method 1
a capacitive circuit element (410) of the circuit arrangement. The rate at which the charges are discarded is dependent on at least one control signal being provided to the circuit arrangement
Implementation Method 2
The rate at which the capacitive circuit element is being discharged can be varied according to a control signal, thereby enabling the weighted operations on the time-mode signals. For example, the proposed concept can be implemented by successively discharging a capacitive circuit element, e.g., via a resistor, and tuning the RC time constant.
Data Source
AI summary
Examples relate to a circuit arrangement, a time-mode arithmetic unit circuit arrangement, an all-digital phase-locked loop, and corresponding methods. A circuit arrangement is configured to discard charges from a capacitive circuit element of the circuit arrangement based on a width of one or more signal pulses of an input signal being provided to the circuit arrangement, with the rate at which the charges are discarded being dependent on at least one control signal being provided to the circuit arrangement. The circuit arrangement is configured to provide an output signal flank having a delay relative to a readout signal flank being provided to the circuit arrangement, with the delay being based on the charges stored in the capacitive circuit element at the time the readout signal flank is provided to the circuit arrangement.