Centralized Timing Controller for Semiconductor Storage Data Bus
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Solution Overview
Problem
Conventional semiconductor storage devices, such as MRAM, face challenges in controlling data transfer timing across memory units sharing a common data bus, leading to potential data overlap due to variations in delay time caused by process variations, which can result in data collisions and inefficient interleaving operations.
Innovation Solution
A centralized timing controller is implemented, shared among memory units, which includes a delay-time unit column and cascade state machines to manage the interleaving operation, ensuring data is transferred without overlap by maintaining consistent delay times across all units, thereby preventing data collisions and optimizing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a delay circuit is provided for each memory unit to control data transfer timing, then data transfer timing can be controlled individually, but delay time varies according to process variations causing data to be transferred in an overlapped manner
Solution Approach 1:
The patent merges the delay circuits into a single shared delay circuit that is commonly used by all memory units. This centralized approach ensures that all memory units receive the same delay time, eliminating the process variation issues that occur when each memory unit has its own separate delay circuit. The shared delay circuit generates a common delay signal that synchronizes data transfer timing across all memory units, preventing overlapping transfers.
Solution Approach 2:
The shared delay circuit serves as a universal timing control mechanism for all memory units simultaneously. Instead of having dedicated delay circuits for each memory unit, the single delay circuit provides timing control services to multiple memory units, ensuring consistent delay time application across the entire system and eliminating variability caused by individual circuit implementations.
2Reliability
If a centralized timing controller is implemented to prevent data overlap, then data transfer reliability is improved, but device complexity increases
Solution Approach 1:
The timing controller is designed as a universal control unit that manages multiple memory units through a single shared delay circuit. This multi-functional approach allows the system to achieve reliable synchronized data transfer without requiring separate delay circuits for each memory unit, thereby reducing overall device complexity while maintaining data transfer reliability.
Data Source
AI summary
A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.