Timing Controller Integrated Nonvolatile Memory for Fast Display Startup
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Solution Overview
Problem
Conventional timing controllers in electronic devices suffer from complex architectures, high power consumption, and slow startup times due to the use of volatile and external non-volatile memories, which complicate the data storage and processing procedures.
Innovation Solution
Integration of a first non-volatile memory within the timing controller to store software code and other data, eliminating the need for external volatile and non-volatile memories, thereby simplifying the architecture, reducing area, and enabling fast startup and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external volatile and non-volatile memories are used in conventional timing controllers, then data storage capacity is sufficient, but device complexity increases and area expands
Solution Approach 1:
The patent integrates both volatile memory (SRAM) and non-volatile memory (Flash) into a single unified memory module within the timing controller. This merging eliminates the need for separate external memory components, thereby reducing device complexity and area while maintaining sufficient data storage capacity for software code and display parameters
2Quantity of substance
If external non-volatile memory is used to store software code, then storage capacity is adequate, but startup time increases due to loading processes
Solution Approach 1:
The patent pre-loads software code from external non-volatile memory into the integrated Flash memory during manufacturing or initial setup. This preliminary action ensures that the software code is already available in the timing controller's internal non-volatile memory, eliminating the need for time-consuming loading processes during startup and thereby reducing startup time
3Speed
If volatile memory is used for data storage, then data access speed is fast, but power consumption increases due to continuous power supply requirement
Solution Approach 1:
The patent employs the integrated non-volatile Flash memory to store data that requires persistence, eliminating the need for continuous power supply to maintain data integrity. The volatile SRAM is used only for temporary data buffering during active operation, thereby reducing overall power consumption while maintaining fast data access speeds when needed
4Adaptability or versatility
If multiple separate memory components are used, then functional requirements are met, but manufacturing complexity increases
Solution Approach 1:
The patent integrates both volatile SRAM and non-volatile Flash memory into a single unified memory module, simplifying the manufacturing process by reducing the number of separate components that need to be assembled and tested. This merging maintains all necessary functional requirements while significantly reducing manufacturing complexity
Data Source
AI summary
A timing controller and a working method thereof, a display module, and an electronic device relate to the field of electronic technologies, and are used for optimizing performance of the timing controller. The timing controller (TCON) includes a first non-volatile memory (NVM1). The first non-volatile memory (NVM1) is configured to store data for working of the timing controller (TCON), such as software code for starting the timing controller (TCON), firmware parameter information, data for demura correction, data for anti-burn-in correction, and data for overdriving compensation. A processor (21), a demura correction circuit (23), an anti-burn-in correction circuit (24), an overdrive circuit (26), and another circuit included in the timing controller (TCON) directly retrieve the data for working from the first non-volatile memory (NVM1).