Timing-Based Layer Assignment for Lower-Delay IC Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional IC design methods face challenges in optimizing layer assignment, leading to increased signal delay and negative impacts on timing due to varying resistance and capacitance values across different routing layers.
Innovation Solution
A timing-based layer assignment process that reassesses the routing path of nets from a first layer to a second layer based on a comparison of delay values, prioritizing layers with lower signal delay to improve timing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If routing is assigned to layers based on conventional methods, then routing completion is achieved, but signal delay increases due to varying resistance and capacitance values across layers
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting layer assignment based on timing parameters. Specifically, it calculates delay values for different layers and reassigns routing paths from layers with higher delay to layers with lower delay, thereby optimizing signal timing characteristics while maintaining routing connectivity
Solution Approach 2:
The invention introduces dynamics by implementing a multi-stage layer assignment process that can adapt and revise layer assignments. The system performs initial layer assignment, then conducts timing analysis, and finally reassigns layers based on timing violations, creating a dynamic optimization process rather than a static single-pass assignment
2Loss of time
If routing paths are reassigned to optimize timing, then signal delay is reduced, but design complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the layer assignment process into distinct stages: initial layer assignment, timing analysis, and iterative reassignment. This segmentation allows the complex optimization problem to be broken down into manageable steps, where each stage focuses on specific aspects of the layer assignment without overwhelming computational complexity
Data Source
AI summary
Aspects of the present disclosure address systems and methods for timing-based layer assignment. Routing is performed on a set of nets of an integrated circuit design. The routing comprises generating a route between a first pin and a second pin of a net. An initial layer assignment is performed on the set of nets based on the routing. The initial layer assignment comprises assigning the route to a first layer of the design based on first preferred routing layer designation. Timing-based layer assignment is performed based on the initial layer assignment. The timing-based layer assignment comprises reassigning the route from the first layer to a second layer based on a second preferred routing layer designation determined based on a comparison of a first delay value associated with the first layer and a second delay value associated with the second preferred routing layer designation.