On-Chip Timing Skew Characterization for Setup and Hold Measurement
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Solution Overview
Problem
Conventional testers lack the resolution to accurately characterize the setup and hold time of synchronous circuits, which is crucial for preventing metastability and ensuring proper operation in high-frequency semiconductor memory chips, as the setup and hold times are typically less than one hundred picoseconds.
Innovation Solution
An on-chip timing skew characterization apparatus comprising a coarse timing skew characterization circuit with multiple coarse delay cells and a fine timing skew characterization circuit with high-speed inverters, allowing for precise adjustment of delay times to determine the minimum setup and hold times of a device-under-test, such as a D-type flip-flop, using a combination of coarse and fine delay steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testers are used to characterize setup and hold time, then the testing process is simple, but the measurement precision is insufficient (cannot resolve ~100 picoseconds)
Solution Approach 1:
The timing skew characterization circuit is divided into multiple delay cells (first delay cell, second delay cell, third delay cell, etc.), each contributing a specific delay amount. By segmenting the total delay into discrete cellular units, the circuit achieves fine-grained measurement resolution of approximately 100 picoseconds, far exceeding conventional tester capabilities.
2Productivity
If the frequency of memory clock signals increases, then the productivity increases, but the setup and hold time becomes shorter (less than one hundred picoseconds)
Solution Approach 1:
The patent replaces external conventional testers with an on-chip timing skew characterization circuit that uses digital logic elements (delay cells, flip-flops, logic gates) to generate and measure timing skew. This substitution enables picosecond-level measurement precision directly integrated with the high-frequency memory circuit, matching the speed requirements of modern high-frequency memory operations.
3Measurement precision
If external conventional testers are used for timing characterization, then the device complexity is low, but the measurement precision is insufficient
Solution Approach 1:
The memory device performs its own timing skew characterization through an on-chip circuit that uses the device's own internal signals (clock signals, data signals) and logic elements. The characterization circuit is self-contained, requiring no external testing equipment, and leverages the device's inherent operational signals to measure setup and hold times with picosecond resolution.
Data Source
AI summary
A timing skew characterization apparatus comprises a coarse timing skew characterization circuit, a fine timing skew characterization circuit and a coarse delay cell calibration circuit. The coarse timing skew characterization circuit comprises a plurality of coarse delay cells whose delays can be calibrated through the coarse delay cell calibration circuit. The calibration of fine delay cells can be implemented through a trail and error process. Both coarse delay step and fine delay step can be characterized through a single measurement setup. As a result, the timing skew characterization apparatus provides a high resolution setup and hold time measurement.