TMD Transistor Heterostructure for Low-Resistance CMOS Contacts
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Solution Overview
Problem
Transition metal dichalcogenide transistors face excessive contact resistance between the channel and source/drain regions, and existing preparation methods are not compatible with industrial CMOS processes, making large-scale production challenging.
Innovation Solution
A transition metal dichalcogenide transistor design featuring a gate, gate dielectric layer, and channel layer structure where the source/drain regions are made of metallic transition metal dichalcogenides and the channel layer is made of semiconductor transition metal dichalcogenides, with a specific layering and doping process to ensure compatibility with CMOS processes and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bulk metal is used for source/drain regions, then electrical conductivity is improved, but contact resistance at the interface with TMD channel increases significantly
Solution Approach 1:
The patent changes the material parameter of the source/drain region from conventional bulk metal to metallic TMD materials (such as 1T-phase MoS2, WTe2, or MoTe2), which have different electronic properties including higher carrier concentration and metallic conductivity. This parameter change reduces the Schottky barrier height at the TMD-channel interface, thereby reducing contact resistance while maintaining high electrical conductivity.
Solution Approach 2:
The patent employs composite material structures where metallic TMD materials are combined with semiconductor TMD channel materials (such as 2H-phase MoS2, WS2, or WSe2). This creates a heterostructure that leverages the metallic properties of the source/drain region for low contact resistance while maintaining the semiconductor properties of the channel for transistor operation, effectively resolving the contradiction between conductivity and contact resistance.
2Reliability
If new materials and device structures are adopted, then performance requirements are improved, but compatibility with existing CMOS process deteriorates
Solution Approach 1:
The patent modifies the material phase parameter of TMD materials to achieve metallic properties in source/drain regions while keeping the channel in semiconductor phase. This parameter change allows the use of standard semiconductor fabrication processes (such as CVD, PVD, and etching) that are already compatible with CMOS manufacturing, thereby maintaining process adaptability while improving device performance.
Solution Approach 2:
The patent segments the TMD material into different functional regions with different phases: metallic TMD for source/drain regions and semiconductor TMD for the channel. This segmentation allows each region to be optimized independently using established fabrication techniques, enabling integration with existing CMOS processes while achieving superior performance through the metallic-semiconductor heterostructure.
3Ease of manufacture
If conventional preparation methods are used, then manufacturing simplicity is maintained, but large-scale production capability is reduced
Solution Approach 1:
The patent employs universal fabrication techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and standard photolithography to create both metallic and semiconductor TMD regions. These multi-functional processes are already widely used in CMOS manufacturing, allowing the same equipment and工艺流程 to produce both research-grade and production-grade devices, thereby enabling large-scale production without sacrificing manufacturing simplicity.
Data Source
AI summary
A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both the sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties. The present invention provides a transition metal dichalcogenide transistor and a preparation method thereof, which can solve a problem of excessive contact resistance between a transition metal dichalcogenide transistor channel and a source/drain region and can make the transition metal dichalcogenide transistor compatible with the existing CMOS process.