TMR Flip-Flop Voting Logic for SEU Fault Tolerance
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Solution Overview
Problem
Existing data flip-flops in safety-related systems, such as automotive and avionics, are susceptible to single event upsets (SEUs) caused by terrestrial radiation, which can compromise system safety and fail to meet stringent fault tolerance requirements like ASIL B, C, and D.
Innovation Solution
A triple modular redundancy (TMR) flip-flop design incorporating master-gate-latch circuits and a voting logic circuit to generate a digital signal based on a majority of redundant flip-flop outputs, with improved power performance area (PPA) and design for testability (DFT) capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional data flip-flops are used in safety-related systems, then the circuit area and power consumption are lower, but the fault tolerance against single event upsets is insufficient
Solution Approach 1:
The flip-flop is divided into multiple independent functional blocks (master latch, slave latch, voting logic) that can be separately implemented and tested. Each latch is further segmented into clocked gates and storage elements, allowing modular design that improves fault tolerance while managing area through systematic decomposition
Solution Approach 2:
A voting logic circuit is introduced as an intermediary component between the master latches and slave latches. This voting circuit receives signals from multiple master latches and generates a corrected output signal, acting as a mediator that eliminates the need for redundant slave latches and reduces overall circuit area while maintaining fault tolerance
2Reliability
If traditional data flip-flops are used in safety-related systems, then the power consumption is lower, but the fault tolerance against single event upsets is insufficient
Solution Approach 1:
The voting logic circuit serves as an intermediary that consolidates the functionality of multiple redundant latches into a single logic block. By receiving signals from multiple master latches and producing a single corrected output, it eliminates the need for multiple slave latches, thereby reducing power consumption while maintaining the fault detection and correction capabilities
Solution Approach 2:
The voting logic circuit merges the functions of multiple redundant slave latches into a single logical unit. Instead of having separate slave latches for each master latch, the voting circuit combines their outputs and generates a unified corrected signal, reducing the total number of active components and associated power consumption
3Reliability
If triple modular redundancy is implemented with multiple slave latches, then the fault tolerance is improved, but the circuit area and power consumption increase
Solution Approach 1:
The voting logic circuit acts as an intermediary that simplifies the overall circuit architecture by replacing multiple complex slave latch structures with a single logic-based voting unit. This intermediary approach maintains the redundancy benefits while reducing the complexity of interconnections and component coordination
Solution Approach 2:
The slave latch functionality is extracted and replaced by a dedicated voting logic circuit. Instead of having each master latch followed by a separate slave latch, the slave latch function is taken out and consolidated into a centralized voting unit that handles the redundancy resolution for all master latches
4Reliability
If existing flip-flop designs are used, then the design is simpler, but the compliance with stringent fault tolerance requirements like ASIL B, C, and D is not achieved
Solution Approach 1:
The flip-flop is segmented into distinct functional modules (master latch with clocked gates, slave latch with clocked gates, voting logic) that can be independently designed, verified, and tested. This segmentation allows each module to be optimized for its specific function while collectively achieving ASIL compliance through systematic fault coverage
Solution Approach 2:
The voting logic circuit implements a feedback mechanism where the outputs of multiple master latches are continuously monitored and compared. When a discrepancy is detected (indicating a potential single event upset), the voting logic generates a corrected output signal, providing real-time feedback that ensures compliance with stringent fault tolerance requirements
Data Source
Figure 1A~1B
Figure 2
Figure 3A~3B
AI summary
A TMR flip-flop (300) includes a set of master-gate-latch circuits (320, 340) including a first set of inputs to receive a first digital signal (D), and a second set of inputs to receive a clock (CLK); and a voting circuit (330) including a set of inputs coupled to a set of outputs of the set of master-gate-latch circuits, and an output to generate a second digital signal based on the first digital signal.