TMR Flip-Flop Voting Circuit for SEU-Tolerant Low-Power Latching
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Solution Overview
Problem
Data flip-flops in safety-critical systems, such as automotive and avionics, are vulnerable to single event upsets (SEUs) caused by terrestrial radiation, which can lead to unintended state changes, compromising system safety and failing to meet stringent failure-in-time (FIT) requirements.
Innovation Solution
A triple modular redundancy (TMR) flip-flop design with improved power performance area (PPA) and design for testability (DFT) capabilities, incorporating master-gate-latch circuits and a voting logic circuit that generates a digital signal based on the majority logic levels of redundant flip-flops to mitigate SEUs and enhance fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional flip-flops are used in safety-critical systems, then the system is simpler and uses less area, but the system becomes vulnerable to SEUs and fails to meet FIT requirements
Solution Approach 1:
The flip-flop is segmented into three identical redundant modules (first, second, and third master-gate-latch circuits), each processing the same input signal independently. This segmentation allows the system to tolerate failures in individual segments while maintaining overall reliability through majority voting in the voting logic circuit.
Solution Approach 2:
The patent applies local quality by making each redundant module identical in structure and function, ensuring that each segment has the same quality characteristics. This uniformity allows the voting logic to reliably determine the correct output by comparing identical structures, improving reliability without requiring complex差异化 design.
2Reliability
If triple modular redundancy is implemented, then fault tolerance improves, but power consumption and area increase
Solution Approach 1:
The patent merges the voting logic circuit with the clocking mechanism by using the same clock signal to synchronize all three redundant modules and the voting process. This merging reduces the need for separate control signals and reduces overall power consumption compared to implementing voting logic with independent control circuits.
Solution Approach 2:
The clock signal serves multiple functions: it clocks the first master-gate-latch circuit, clocks the second master-gate-latch circuit, clocks the third master-gate-latch circuit, and enables the voting logic circuit. This multi-functionality reduces the number of separate control signals needed, thereby reducing power consumption while maintaining fault tolerance.
Data Source
AI summary
A triple modular redundancy (TMR) flip-flop includes a set of master-gate-latch circuits including a first set of inputs to receive a first digital signal, and a second set of inputs to receive a clock; and a voting logic circuit including a set of inputs coupled to a set of outputs of the set of master-gate-latch circuits, and an output to generate a second digital signal based on the first digital signal. Another TMR flip-flop includes a set of master-gate-latch circuits to receive a set of digital signals in response to a first edge of a clock, respectively; and latch the set of digital signals in response to a second edge of the clock, respectively; and a voting logic circuit to receive the latched set of digital signals; and generate a second digital signal based on a majority of logic levels of the latched first set of digital signals, respectively.