Through-Mold Vias for High I/O Density in QFP Packages
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Solution Overview
Problem
Conventional semiconductor device packages face challenges in increasing input/output (I/O) pins without correspondingly increasing the package footprint, which is undesirable, especially in applications like quad-flat packages (QFP), and existing methods like inward lead bending are complex.
Innovation Solution
The implementation of through-mold-vias (TMVs) extending in a molding compound using laser direct structuring (LDS) processing to form additional leads at the rear or bottom side of the package, allowing for increased I/O without enlarging the package dimensions, facilitated by LDS-based multiple-row QFP packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional leads are bent inward near the package plastic body to increase I/O number, then the I/O number increases, but the process complexity increases due to additional complex bending process
Solution Approach 1:
The patent introduces through-mold vias that extend vertically through the molding compound from the front surface to the rear surface, utilizing the third dimension (depth) to create additional I/O connections. This allows leads to be formed in multiple rows including front-side leads, rear-side leads, and intermediate leads, all accessible through different surfaces of the package without requiring complex bending operations.
Solution Approach 2:
The patent replaces the mechanical lead bending process with a molding process that forms through-mold vias directly during package encapsulation. The vias are created by injecting molding compound through cavities in the mold, eliminating the need for subsequent mechanical bending operations and reducing process complexity.
2Quantity of substance
If conventional lead bending method is used to increase I/O number, then the I/O number increases, but manufacturing simplicity deteriorates due to additional complex bending process
Solution Approach 1:
The patent combines the lead formation process with the package encapsulation molding process. The through-mold vias are formed simultaneously with the molding compound injection, merging two separate operations (lead formation and packaging) into one integrated process, thereby simplifying manufacturing.
Solution Approach 2:
The patent performs lead formation in advance during the molding process itself, rather than as a subsequent operation. The molding compound is injected through cavities to form vias that will become the leads, preparing the electrical connections before the package is completed and removed from the mold.
3Quantity of substance
If I/O number is increased in conventional QFP packages, then the I/O number increases, but the package footprint increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming through-mold vias that extend through the thickness of the molding compound. This allows additional I/O connections to be made in intermediate rows between the front and rear surfaces, effectively using the third dimension to increase I/O density without expanding the horizontal package footprint.
Solution Approach 2:
The patent nests multiple rows of leads within the vertical thickness of the package by forming through-mold vias in intermediate positions between the front and rear lead rows. This nested arrangement of leads at different depths allows higher I/O density within the same external dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a higher I/O number while maintaining or reducing the package footprint, simplifying the process compared to traditional lead bending methods, and is detectable through external inspection and cross-section analysis.
Implementation Method 1
Laser direct structuring (LDS) processing can be used to form these vias as well as further electrical connections to the chip or chips
Data Source
AI summary
A semiconductor chip is arranged on a first surface of a die pad in a substrate (leadframe) including an array of electrically conductive leads. An encapsulation of laser direct structuring (LDS) material encapsulates the substrate and the semiconductor chip. The encapsulation has a first surface, a second surface opposed to the first surface and a peripheral surface. The array of electrically conductive leads protrude from the peripheral surface with areas of the second surface of the encapsulation arranged between adjacent leads. LDS structured areas of the second surface located between adjacent leads in the array of electrically conductive leads provide a further array of electrically conductive leads exposed at the second surface. First and second electrically conductive vias extending through the encapsulation material as well as electrically conductive lines over the encapsulation material provide an electrical bonding pattern between the semiconductor chip and selected ones of the leads.