Inter-chip Bonding Wire Routing for ToF Sensor Charge Distribution
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Solution Overview
Problem
In sensor devices using the indirect time-of-flight method, inaccurate operation of transfer gate elements leads to inadequate charge distribution to floating diffusions, resulting in deteriorated distance measurement performance.
Innovation Solution
The sensor device employs inter-chip bonding wires formed by copper-copper connection, with equal wire resistances and cross-sectional areas, and strategically arranged to minimize line-to-line capacitance, ensuring balanced drive signal waveforms and accurate charge distribution between transfer gate elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different types of wires are used for transfer gate elements and ground, then wire functions are optimized, but wire resistance differences cause impedance mismatch and deteriorate charge distribution accuracy
Solution Approach 1:
The patent applies homogeneity by using the same type of wire (first wire, second wire, and third wire all use identical wire types, materials, and structures) to connect the first transfer gate element, second transfer gate element, and ground respectively. This ensures that wire resistances are substantially equal, preventing impedance mismatch and maintaining accurate charge distribution between the two floating diffusions in the indirect ToF sensor device.
2Reliability
If wire lengths are made equal to reduce resistance differences, then charge distribution improves, but device area increases
Solution Approach 1:
The patent resolves the area conflict by transitioning from planar wire routing to three-dimensional routing. Wires are routed through multiple layers (first wire formation layer, second wire formation layer) and utilize vertical connections (conductive plugs, vias) to achieve equal effective lengths without increasing the device footprint. This dimensional approach allows precise resistance matching while maintaining compact sensor device area.
3Measurement precision
If symmetric wire arrangement is used to minimize capacitance differences, then measurement precision improves, but wiring complexity increases
Solution Approach 1:
The patent employs asymmetric wiring structures where the first wire and second wire are positioned at different locations and orientations relative to the pixel array, yet achieve equal effective lengths through strategic routing in multiple layers. The third wire (ground) is positioned to balance the capacitance distribution. This controlled asymmetry minimizes line-to-line capacitance differences between signal wires while maintaining overall wiring manageability and avoiding excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the accuracy of transfer gate element operation, improving distance measurement performance by preventing impedance mismatch and ensuring precise charge distribution, thereby enhancing the overall measurement accuracy.
Implementation Method 1
the reflected light from the object is photoelectrically converted by a photoelectric conversion element such as a photodiode
Implementation Method 2
each of the first wire, the second wire, and the third wire is formed by bonding a first portion formed in the first wire formation layer and extending in a first direction and a second portion formed in the second wire formation layer and extending in the first direction
Data Source
AI summary
A sensor device according to the present technology includes a first chip including a first semiconductor substrate and a first wire formation layer and including a pixel that includes a photoelectric conversion element, and a first transfer gate element and a second transfer gate element configured to transfer accumulated charges of the photoelectric conversion element, and a second chip including a second semiconductor substrate and a second wire formation layer, in which a first wire electrically connected to the first transfer gate element, a second wire electrically connected to the second transfer gate element, and a third wire electrically connected to a ground are formed, and each of the first wire, the second wire, and the third wire is formed by bonding a first portion formed in the first wire formation layer and extending in a first direction and a second portion formed in the second wire formation layer and extending in the first direction.