Token-Based VLIW Asynchronous Processor Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing asynchronous processor architectures face inefficiencies in processing longer instructions, leading to increased latency and delays due to resource contention and structural hazards, particularly when handling very long instruction words (VLIWs).
Innovation Solution
The implementation of a token-based Very Long Instruction Word (VLIW) architecture, where multiple instruction bundles are processed simultaneously by sets of arithmetic and logic units (ALUs) arranged in series or parallel, using token rings to manage resource access and reduce contention, with a feedback engine distributing instructions and a crossbar bus transferring calculation information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional asynchronous processor architecture is used to process longer instructions, then instruction processing capability is improved, but latency and delay increase
Solution Approach 1:
The processor divides long instructions into multiple instruction bundles, with each bundle containing multiple micro-instructions that can be processed independently by different ALU sets. This segmentation allows parallel processing of instruction portions, improving throughput while maintaining manageable latency for each individual bundle.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing multiple sets of ALUs (first set, second set, third set) that can simultaneously process different instruction bundles. This multi-dimensional parallel processing architecture enables longer instructions to be processed across multiple processing dimensions, reducing overall latency.
2Productivity
If multiple ALUs access shared resources simultaneously, then processing throughput is improved, but resource contention increases
Solution Approach 1:
Token processing logic is introduced to预先 allocate and manage resource access rights before ALUs attempt to access shared resources. The token mechanism grants exclusive access permissions in advance, preventing contention by ensuring that only one ALU set can access a particular resource at any given time, while maintaining high throughput through efficient token passing.
3Productivity
If instruction bundles are processed in parallel by multiple ALU sets, then system performance is improved, but structural hazards increase
Solution Approach 1:
The patent introduces bundle registers and token processing logic as intermediary components between the feedback engine and ALU sets. These intermediaries buffer and coordinate instruction bundle distribution, preventing structural hazards by ensuring proper synchronization and resource allocation before parallel processing occurs, thereby maintaining system reliability.
Data Source
AI summary
Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.