Top Electrode Last RRAM Cell Structure Preventing Metal Redeposit
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Solution Overview
Problem
The formation of resistive random access memory (RRAM) cells is hindered by the re-deposition of conductive material from the top electrode layer onto the sidewalls during etch processes, leading to electrical shorts and rendering the memory cell inoperable.
Innovation Solution
The top electrode layer is formed after patterning the memory cell stack, with an etch stop layer and masking layer used to prevent re-deposition, and a top electrode is formed within the inter-metal dielectric (IMD) layer to contact the top metal layer, thereby preventing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the top electrode layer is formed before patterning the memory cell stack, then the top electrode can be properly positioned, but conductive material re-deposits onto sidewalls during etching causing electrical shorts
Solution Approach 1:
The top electrode layer is formed in advance before the memory cell stack is patterned. This preliminary formation allows the electrode material to be deposited uniformly across the substrate, ensuring proper positioning and coverage. The electrode layer serves as a sacrificial layer during subsequent etching processes, preventing material re-deposition onto sidewalls while maintaining electrical isolation between adjacent cells.
Solution Approach 2:
The top electrode layer acts as an intermediary sacrificial layer between the memory cell stack and the sidewalls. During etching, this layer absorbs and traps any re-deposited conductive material that would otherwise contaminate the sidewalls and cause electrical shorts. The sacrificial layer is later removed after serving its protective function.
2Manufacturing precision
If etching is performed to pattern the memory cell stack, then precise cell definition is achieved, but conductive material re-deposits onto sidewalls rendering cells inoperable
Solution Approach 1:
The potential harmful effect of conductive material re-deposition during etching is converted into a beneficial protective mechanism. By intentionally having the top electrode layer in place before etching, any re-deposited material is captured on this layer rather than on the critical sidewalls of the memory cell stack. This transforms what would be a defect into a protective sacrificial function.
Solution Approach 2:
The top electrode layer serves as an intermediary barrier during the etching process. It mediates between the etching environment and the memory cell stack sidewalls, absorbing any stray conductive material that escapes during etching. This intermediary layer protects the sidewalls from contamination while allowing precise cell definition to be achieved.
3Reliability
If the top electrode is formed within the inter-metal dielectric layer, then electrical shorts are prevented, but additional processing steps are required
Solution Approach 1:
The formation of the top electrode within the inter-metal dielectric layer is merged with the existing dielectric deposition and planarization processes. By integrating the electrode formation into the dielectric layer processing sequence, the patent avoids adding significant complexity while achieving reliable electrical isolation. The electrode is formed as part of the inter-metal dielectric structure rather than as a separate, standalone component.
Solution Approach 2:
The inter-metal dielectric layer serves multiple functions: it provides electrical isolation between metal layers, contains the top electrode structure, and prevents electrical shorts. By making the dielectric layer multi-functional and integrating the electrode formation within it, the patent reduces the need for additional dedicated isolation structures and processing steps.
Data Source
AI summary
An integrated chip comprising a memory cell is provided. The memory cell is disposed over a substrate and comprises a data storage layer between a top metal layer and a bottom metal layer. An etch stop layer overlies the top metal layer. An upper dielectric layer overlies the etch stop layer. Outer sidewalls of the etch stop layer, outer sidewalls of the upper dielectric layer, and outer sidewalls of the top metal layer are aligned. A top electrode overlies the memory cell. The top electrode directly contacts inner sidewalls of the top metal layer, inner sidewalls of the etch stop layer, and inner sidewalls of the upper dielectric layer.