Top-Gate Oxide Array Substrate Layout for Short-Channel Stability
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Solution Overview
Problem
In oxide semiconductor array substrates manufactured by a top gate self-alignment process, carriers easily diffuse below the gate insulating layer, causing parasitic capacitance and short channel effects, which lead to instability and low aperture ratios and resolutions in TFT devices.
Innovation Solution
The array substrate design includes a substrate with an oxide semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source-drain electrode metal layer, where the gate electrode is formed with a smaller size through a two-stage interlayer insulating layer manufacturing process, preventing carrier diffusion under the gate electrode and maintaining channel region length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If carriers in conductive regions are made conductive with the top gate self-aligning process, then the conductive regions can be formed, but carriers are easily diffused to non-conductive regions in subsequent thermal processes, resulting in parasitic capacitance and short channel effects
Solution Approach 1:
The patent extracts the gate electrode from overlapping with the conductive regions by positioning it only over the channel region. This separation removes the source of parasitic capacitance (the gate electrode) from its harmful interaction with the conductive regions, while still maintaining the necessary electrical connection through the gate insulating layer for channel control.
Solution Approach 2:
The patent performs preliminary positioning of the gate electrode before carrier diffusion occurs in subsequent thermal processes. By pre-establishing the gate electrode's position exclusively over the channel region, the design prevents carriers from diffusing into areas where they would create parasitic capacitance with the gate electrode.
2Ease of manufacture
If the gate metal layer is made larger to ensure proper alignment, then the manufacturing process is simplified, but the design space increases, resulting in low aperture ratio and low resolution
Solution Approach 1:
The patent applies local quality by making the gate insulating layer extend beyond the gate electrode in specific areas (over the conductive regions) while keeping the gate electrode itself compact and aligned only with the channel region. This localized extension provides alignment tolerance without increasing the overall gate metal layer area, thus maintaining high aperture ratio and resolution.
3Quantity of substance
If carriers diffuse below the gate insulating layer, then conductive regions can be formed, but the effective channel region length becomes shorter, causing instability of devices
Solution Approach 1:
The patent extracts the gate electrode from the area where carrier diffusion occurs (the conductive regions). By positioning the gate electrode only over the channel region and not over the conductive regions, the design allows carriers to diffuse freely into the conductive regions without creating parasitic capacitance, while the gate electrode continues to effectively control the channel region length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the stability of TFT devices by avoiding parasitic capacitance and short channel effects, enhancing the aperture ratio and resolution of the array substrate.
Implementation Method 1
a gate insulating layer disposed on a side of the oxide semiconductor layer away from the substrate; wherein edges of the gate insulating layer are respectively overlapped with the conductive regions on the both sides of the channel region
Implementation Method 2
a gate electrode disposed on a side of the gate insulating layer away from the substrate; an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate
Data Source
AI summary
The present disclosure provides an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes an oxide semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source-drain electrode metal layer located on a substrate. Wherein the oxide semiconductor layer includes a channel region and conductive regions, the gate insulating layer is respectively overlapped with the conductive regions on both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate.