Top Oxide Planarization via Chemical Etching to Prevent CMP Scratching
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in achieving the required planarity and uniformity for integrated circuit chips with high integration density, particularly due to issues like scratching and dishing during chemical-mechanical polishing (CMP), which compromise manufacturing yield and lead to defects such as picture frame defects and foreign material faults.
Innovation Solution
A method involving deglazing to reduce the height difference between differentiated areas, using a polysilicon hard mask for improved control, and employing ARC-assisted planarization with non-selective etching to achieve a planar surface with a tolerance of less than 15 nm, thereby avoiding mechanical damage and enhancing manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical-mechanical polishing (CMP) is used for planarization, then a planar surface is achieved, but scratching and dishing defects occur that compromise manufacturing yield
Solution Approach 1:
The patent replaces the mechanical polishing action of CMP with a purely chemical etching process. A planarizing agent is deposited and then selectively etched to remove high spots, achieving planarity without mechanical contact that causes scratching and dishing. This substitutes mechanical removal with chemical removal mechanisms.
Solution Approach 2:
The patent introduces a planarizing agent as an intermediary material layer. This agent is deposited over the topography variations, then etched away after performing its planarization function. The agent mediates between the rough underlying structure and the requirement for a planar surface, enabling planarity achievement without direct mechanical action on the substrate.
2Device complexity
If array top oxide is formed after polysilicon gates (TOL process), then fewer masks are required, but chemical-mechanical polishing is needed which causes scratching damage
Solution Approach 1:
The patent replaces the mechanical polishing step in the TOL process with a chemical etching approach. Instead of using CMP to planarize the polysilicon gates, a planarizing agent is deposited and chemically etched to remove excess material, achieving planarity without mechanical contact that would scratch or damage the polysilicon gate structures.
3Productivity
If integration density is increased, then performance and functionality improve, but planarity control becomes more difficult and defects increase
Solution Approach 1:
The patent replaces mechanical polishing with chemical etching using a planarizing agent. This chemical approach provides better control over material removal at the fine dimensions required for high integration density, avoiding the scratching and dishing defects that compromise planarity control in dense circuits.
Solution Approach 2:
The planarizing agent acts as a temporary copy or surrogate for the final planar surface. It is deposited to fill topography variations, then etched away after transferring the planarity requirement to the underlying structures, enabling precise planarity control needed for high integration density without direct mechanical intervention.
4Reliability
If top oxide is formed early (TOE process), then isolation is achieved, but more masks are required compared to TOL process
Solution Approach 1:
The patent extracts the planarization function from the main fabrication sequence by using a separate planarizing agent deposition and etching step. This allows the TOE process to achieve its isolation quality benefits while the planarization is handled independently, potentially reducing the need for additional masks in the main process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves manufacturing yield by reducing defects and achieving the necessary planarity and uniformity, especially in processes like TOE, TON, and TOL, while avoiding mechanical damage and the limitations of CMP, particularly in high-density integrated circuits.
Implementation Method 1
depositing a planarizing agent to the body of material to form a substantially planar surface
Implementation Method 2
performing a non-selective etching to a point on or within the body of material
Data Source
AI summary
Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.