Top-to-bottom interconnects for flip-chip IC packages
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Solution Overview
Problem
Integrated-circuit chip packages face challenges in maximizing interconnect density due to the valuable real estate required by die-side interconnects, which limits the compactness and efficiency of power delivery and signal integrity in flip-chip configurations.
Innovation Solution
The implementation of top-to-bottom (T2B) interconnects, which include a molded lead frame with folded interconnects that shunt around the integrated-circuit package substrate, allowing for nested and ganged configurations that increase pin count while minimizing package size, and utilize underfill materials for protection, enabling efficient power and signal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die-side interconnects are used in flip-chip configurations, then electrical connections are established between the die and substrate, but valuable die-side real estate is consumed limiting compactness and interconnect density
Solution Approach 1:
The patent introduces top-to-bottom interconnects that extend vertically through the package substrate from the top surface to the bottom surface, utilizing the third dimension (depth/height) rather than consuming horizontal die area. This dimensional transition allows interconnects to pass through the substrate without occupying valuable die-side real estate, thereby resolving the contradiction between connection reliability and area consumption.
Solution Approach 2:
The folded interconnect structure is nested within the package substrate, with the interconnect trace folding back on itself and being embedded within the substrate layers. This nesting approach allows the interconnect to occupy minimal external space while maintaining its electrical connection function, effectively resolving the area consumption issue.
2Adaptability or versatility
If more interconnects are added to increase pin count, then functionality is enhanced, but package size increases
Solution Approach 1:
By transitioning from planar interconnect layouts to three-dimensional folded interconnects that extend through the substrate height, the patent enables increased pin count without proportional increases in package footprint. The vertical dimension provides additional space for routing multiple interconnects.
Solution Approach 2:
The folded interconnect configuration allows multiple interconnect traces to be nested within the same horizontal footprint by folding them vertically through the substrate. This nesting enables higher pin density without increasing the overall package size.
3Quantity of substance
If folded interconnects are implemented to increase density, then interconnect density is enhanced, but manufacturing complexity increases
Solution Approach 1:
The folded interconnect structure is pre-formed and integrated into the package substrate during the substrate manufacturing process, rather than being added as a separate complex assembly step. This preliminary action reduces manufacturing complexity by incorporating the folded geometry into the standard substrate fabrication workflow.
Solution Approach 2:
The patent merges the folded interconnect structure with the package substrate as an integrated component, combining what could be separate manufacturing steps into a unified structure. This integration simplifies manufacturing by reducing the number of discrete assembly operations required.
Data Source
AI summary
Disclosed embodiments include folded, top-to-bottom interconnects that couple a die side of an integrated-circuit package substrate, to a board as a complement to a ball-grid array for a flip-chip-mounted integrated-circuit die on the die side. The folded, top-to-bottom interconnect is in a molded frame that forms a perimeter around an infield to receive at least one flip-chip IC die. Power, ground and I/O interconnections shunt around the package substrate, and such shunting includes voltage regulation that need not be routed through the package substrate.