TOPCon Solar Cell Electrode Layout That Preserves Passivation
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Solution Overview
Problem
The existing solar cell manufacturing process faces challenges in maintaining the passivation effect on the substrate surface due to electrode penetration through the tunneling oxide layer, leading to increased carrier recombination and reduced photoelectric conversion efficiency.
Innovation Solution
A solar cell design incorporating a tunneling oxide layer, a doped conductive layer, an intrinsic polycrystalline silicon layer, and electrodes where the electrodes are partially located within the intrinsic polycrystalline silicon layer, creating a gap between the electrode top end and the substrate to prevent penetration, along with a passivation layer to enhance the interface passivation effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the electrode penetrates through the tunneling oxide layer to contact the substrate, then the electrical connection is improved, but the passivation effect on the substrate surface is destroyed, increasing carrier recombination
Solution Approach 1:
The patent introduces an intrinsic polycrystalline silicon layer as an intermediary between the electrode and the substrate. This intermediate layer allows the electrode to make electrical contact while preventing direct penetration through the tunneling oxide layer, thus maintaining the passivation effect and reducing carrier recombination at the substrate surface.
Solution Approach 2:
The patent changes the contact dimension by having the electrode contact the intrinsic polycrystalline silicon layer rather than directly penetrating to the substrate. This dimensional adjustment in the layer structure allows electrical connection without compromising the passivation function of the tunneling oxide layer.
2Reliability
If the tunneling oxide layer is made thinner to improve carrier tunneling, then the electrical conductivity is improved, but the passivation effect is weakened
Solution Approach 1:
The intrinsic polycrystalline silicon layer serves as a mediator that enables carrier tunneling through the tunneling oxide layer without requiring the layer to be made thinner. This maintains the integrity and passivation function of the oxide layer while still achieving effective electrical conduction.
Solution Approach 2:
The patent changes the structural parameters by adding the intrinsic polycrystalline silicon layer with specific thickness and properties, allowing the tunneling oxide layer to maintain its original thickness and passivation function while achieving the desired electrical conductivity through the combined structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces carrier recombination, improves photoelectric conversion efficiency, and minimizes optical loss by maintaining the passivation effect, thereby enhancing both front and back cell efficiencies and the double-sided power generation rate of the solar cell.
Implementation Method 1
a tunneling oxide layer and a doped conductive layer may generally be manufactured on the surface of the substrate to enhance the passivation effect
Implementation Method 2
Solar cells can directly convert solar radiation energy into electrical energy
Implementation Method 3
a doped conductive layer covering a surface of the tunneling oxide layer away from the substrate
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
A solar cell and a photovoltaic module. The solar cell includes: a substrate including a first surface; a tunneling oxide layer covering the first surface; a doped conductive layer covering a surface of the tunneling oxide layer away from the substrate; an intrinsic polycrystalline silicon layer formed on one side of the doped conductive layer away from the tunneling oxide layer; and a plurality of first electrodes arranged on one side of the intrinsic polycrystalline silicon layer away from the doped conductive layer and electrically connected to the doped conductive layer. At least a portion of the first electrode is located in the intrinsic polycrystalline silicon layer, and a gap is defined between a top end of the first electrode and the substrate.