Trace Cache Next Fetch Prediction With Stable-Branch Filtering
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Solution Overview
Problem
Trace caches in traditional processor designs face challenges due to high power consumption and area usage, particularly when branches unexpectedly exit the cache, which has impeded their practical implementation.
Innovation Solution
Implementing control circuitry to restrict trace caches to store only 'stable' branches that meet a bias threshold, allowing only internal control transfer instructions that are predicted to consistently follow a certain direction, reducing the size of the trace cache needed and improving performance by ensuring the entire trace is executed when hit, while sharing branch predictor circuitry for both instruction and trace caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If trace cache stores all branches including unstable ones, then coverage is improved, but power consumption and area increase substantially
Solution Approach 1:
The patent applies local quality by differentiating between stable and unstable branches, storing only stable branches in the trace cache. This selective approach ensures that the cache contains only high-probability trace continuations, improving power efficiency by avoiding storage and retrieval of unlikely branches while maintaining adequate coverage for predictable execution paths.
Solution Approach 2:
The patent changes the parameter of branch selection by introducing a stability criterion based on branch prediction accuracy. By filtering branches according to their stability characteristics (prediction confidence), the system transforms the trace cache from storing all branches to storing only those meeting stability thresholds, thereby reducing power consumption while maintaining effective coverage.
2Adaptability or versatility
If trace cache stores all branches including unstable ones, then coverage is improved, but area usage increases substantially
Solution Approach 1:
The patent applies local quality by differentiating between stable and unstable branches, storing only stable branches in the trace cache. This selective approach ensures that the cache contains only high-probability trace continuations, reducing area usage by excluding storage for unstable branches that would rarely be executed anyway.
Solution Approach 2:
The patent changes the parameter of branch selection by introducing a stability criterion, transforming the trace cache from storing all branches to storing only stable ones. This parameter-based filtering reduces the cache size and processor area requirements while maintaining coverage for the most important execution paths.
3Productivity
If trace cache is implemented with traditional designs, then instruction fetch bandwidth is improved, but power consumption and area costs increase
Solution Approach 1:
The patent applies local quality by selectively caching only stable branches, which are the most frequently executed paths. This approach maintains high instruction fetch bandwidth by ensuring that the trace cache contains the most valuable trace continuations, while reducing power consumption by avoiding the overhead of managing and retrieving unstable branches.
Solution Approach 2:
The patent changes the selection parameter from inclusive (all branches) to selective (stable branches only), optimizing the trade-off between fetch bandwidth and power consumption. By filtering based on stability, the system achieves efficient bandwidth utilization with reduced power overhead.
4Productivity
If trace cache is implemented with traditional designs, then instruction fetch bandwidth is improved, but processor area increases
Solution Approach 1:
The patent applies local quality by differentiating between stable and unstable branches, storing only stable branches in the trace cache. This selective approach maintains instruction fetch bandwidth by ensuring the cache contains high-value trace continuations, while reducing processor area by excluding storage for unstable branches.
Data Source
AI summary
Disclosed techniques relate to next fetch predictor circuitry configured to operate in conjunction with a trace cache. The trace cache circuitry may identify and store traces of instructions based on predicted directions of one or more control transfer instructions. Trace next fetch predictor circuitry may predict a next fetch address based on a current fetch address for a current cycle, which may include predicting a next fetch address following execution of a first trace stored in the trace cache circuitry. The first trace may include multiple fetch groups and multiple control transfer instructions. Arbitration circuitry may select from among multiple predictors and the trace next fetch predictor may have priority in response to a trace cache hit. Disclosed techniques may advantageously improve overall fetch bandwidth in the context of trace cache hits.