Trace Compression Method for Debug Interface Using Register Delta Packing
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Solution Overview
Problem
The increasing complexity of system-on-chip (SOC) devices and the need for pre-silicon design verification pose challenges in debugging and tracing, as traditional methods are inefficient and time-consuming, especially when dealing with multi-core designs and heterogeneous platforms, making it difficult to identify bugs and requiring extensive iterative simulations.
Innovation Solution
The Eidetic platform provides an Embedded Infrastructure for Debug and Trace Interface (EIDETIC) with a proprietary embedded DSP core, employing a trace compression method that calculates differences in register contents and program counter sequences to optimize debug and trace interfaces, achieving high compression rates and reducing bug allocation difficulty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional debug and trace methods are used for complex SOC devices, then complete debugging information can be obtained, but the debug turnaround time becomes excessively long and the system complexity increases
Solution Approach 1:
The patent extracts only the essential debugging information by calculating differences between consecutive register contents and program counter values. Instead of transmitting complete register states, only changed values are captured and transmitted, significantly reducing the data volume while maintaining debugging effectiveness.
Solution Approach 2:
The patent inverts the traditional approach by not transmitting the actual register values directly, but rather transmitting the differences (deltas) between consecutive values. This inversion reduces the amount of data that needs to be transmitted and processed, thereby reducing debug turnaround time.
2Loss of information
If all register contents and program counter values are transmitted without compression, then complete trace data is available, but the data transmission volume and processing overhead increase significantly
Solution Approach 1:
The patent extracts only the essential debugging information by calculating differences between consecutive register contents and program counter values. Instead of transmitting complete register states, only changed values are captured and transmitted, significantly reducing the data volume while maintaining debugging effectiveness.
Solution Approach 2:
The patent changes the parameter representation from absolute values to differential values. By transmitting the difference between consecutive register contents and PC values rather than the absolute values themselves, the data volume is reduced while preserving the ability to reconstruct complete trace information.
3Measurement precision
If detailed tracing of all registers and program counters is performed, then comprehensive debug information is obtained, but the device complexity and resource overhead increase
Solution Approach 1:
The patent extracts only the essential debugging information by calculating differences between consecutive register contents and program counter values. Instead of transmitting complete register states, only changed values are captured and transmitted, significantly reducing the data volume while maintaining debugging effectiveness.
Solution Approach 2:
The patent segments the trace data transmission into two parts: program counter information and register content information. Each type of information is processed and transmitted separately with its own compression logic, allowing for more efficient resource management and reduced overall system complexity.
Data Source
AI summary
The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for storing data. The trace compression method comprises the steps of: (1) finding register content of each of the registers in a first cycle and register content of each of the registers in a second cycle, in which the second cycle is next to the first cycle; (2) calculating difference of the register content of each of the registers in the second cycle and the register content of each of the registers in the first cycle; and (3) packing the differences of the register contents into data trace packets, in which the differences of the register contents of adjacent registers are condensed into a single data trace packet when the differences of the register contents of the adjacent registers are zeroes.


