Tracking Wordline Voltage Suppression for Worst-Case Memory Timing

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Solution Overview

Problem

Existing semiconductor memory technologies face challenges in optimizing read and write operations due to process, voltage, and temperature variability, leading to inefficiencies in sense amplifier timing and memory performance.

Innovation Solution

Implementing a tracking cell system that models the slowest memory cell by using a suppressed tracking wordline voltage and mimicked wordline load to simulate the timing of slower memory cells, thereby eliminating unnecessary delays and improving memory speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the sense amplifier is enabled too soon after driving the wordline, then the memory operation speed is improved, but the memory cell may be read incorrectly

Engineering Contradiction:
Improvememory operation speedVSAvoidread accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The tracking cell is activated in advance with a suppressed wordline voltage to predict the timing characteristics of the slowest memory cell. This preliminary action allows the system to determine the optimal sense amplifier enable time before actual memory operations, ensuring both speed and accuracy by preventing premature sense amplifier activation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A tracking cell is used as a simplified copy of the memory cell to model the timing behavior of the slowest cell in the array. By copying the essential timing characteristics through the tracking cell with suppressed voltage, the system can determine accurate timing parameters without having to wait for actual memory cell responses, thus improving speed while maintaining reliability.

Inventive Principle:
Principle #26Copying

2Reliability

If the sense amplifier enablement is delayed to ensure accurate reading, then the read accuracy is improved, but the memory operation becomes slower

Engineering Contradiction:
Improveread accuracyVSAvoidmemory operation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The tracking cell performs preliminary timing characterization by simulating the slowest memory cell behavior under suppressed voltage conditions. This advance prediction eliminates the need for excessive delays in sense amplifier enablement, as the optimal timing is determined beforehand, thus maintaining high read accuracy without sacrificing speed.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If the tracking wordline voltage is reduced to model slower memory cells, then the timing accuracy for worst-case cells is improved, but the power consumption decreases

Engineering Contradiction:
Improvetiming accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The tracking wordline voltage is changed to a suppressed level that specifically models the timing characteristics of the slowest memory cell. This parameter change in voltage allows the tracking cell to accurately predict worst-case timing scenarios with high precision, while the reduced voltage inherently lowers power consumption compared to full-strength wordline driving.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If excessive delays are introduced to account for slow memory cells, then the timing coverage for all PVT corners is improved, but the overall memory performance deteriorates

Engineering Contradiction:
Improvetiming coverageVSAvoidmemory performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Instead of applying uniform excessive delays to all memory operations, the tracking cell enables precise local timing adjustment. By modeling only the slowest cell's characteristics with suppressed voltage, the system determines the exact delay needed for worst-case scenarios, applying only the necessary timing coverage without introducing unnecessary delays that would degrade overall memory performance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12567460B2Tracking worst case memory cells by suppressing tracking wordline voltage
Publication Date: 2026.03.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12567460B2 patent drawing
  • US12567460B2 patent drawing
  • US12567460B2 patent drawing

AI summary

A memory macro includes a tracking wordline driver that drivers a wordline with a suppressed voltage. The suppressed voltage is made lower than the voltage used to drive wordlines in the memory array by an amount that a tracking wordline is driven with a suppressed voltage, which is a voltage that is held below the drain supply voltage. Suppressing the voltage on the tracking wordline causes tracking memory cell with average cell characteristic to emulate the slowest memory cells in a memory array. The tracking wordline with the suppressed voltage may be subjected to a mimicked wordline load. The tracking wordline with the suppressed voltage and the mimicked wordline load may also be used to enable a mimicked write drive used in write tracking. The tracking wordline with the suppressed voltage may also be used as input to a write delay circuit that times write operations.