Transactional Memory 24-BIT Lookup for Network Processor Throughput
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Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently handling increased throughput requirements due to limitations in processing power and memory access, particularly in identifying data structures using hash functions and logging packet and byte count information.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a novel transactional memory with a configurable Command/Push/Pull (CPP) data bus and dedicated hardware circuits, including an atomic engine and a stats engine, to perform Atomic Look-up, Add, and Lock (ALAL) commands, Stats Add-and-Update (AU) commands, and lookup operations using a hardware trie structure, optimizing hash table operations and packet counting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple microengines are employed to increase processing power, then throughput is improved, but device complexity and memory contention increase
Solution Approach 1:
The system is divided into multiple independent microengines (processing units) that can operate simultaneously on different packet data. Each microengine has its own program counter and registers but shares common resources through the CPP bus, allowing parallel processing while maintaining individual control streams.
Solution Approach 2:
Multiple microengines are merged into a single integrated circuit chip with shared memory resources and a common CPP bus interconnect. This consolidation allows multiple processing units to work together efficiently while reducing the need for separate physical devices, thereby increasing throughput without linearly increasing overall system complexity.
2Speed
If hash table operations are performed using conventional memory access, then data structure identification is achieved, but processing speed is limited by memory access bottlenecks
Solution Approach 1:
The CPP bus enables continuous data transfer between microengines and memory resources without idle cycles. The pull and push operations allow data to be fetched and stored in continuous streams, eliminating wait states and keeping processing units constantly utilized, thereby maintaining high processing speed and throughput simultaneously.
Solution Approach 2:
The CPP bus acts as an intermediary between microengines and memory resources, providing a high-speed communication channel that mediates data access. This intermediary bus with separate command and data paths reduces contention by allowing multiple operations to be pipelined and executed concurrently, overcoming traditional memory access bottlenecks.
3Reliability
If packet count and byte count information are logged to memory, then statistics are maintained, but memory access time and processing delay increase
Solution Approach 1:
Counters for packet and byte counts are pre-configured in the microengine registers and are updated atomically during packet processing. The statistics are accumulated in registers first, then written to memory in batch operations rather than accessing memory for every single count update, thereby maintaining accurate statistics while minimizing memory access time and processing delay.
4Device complexity
If a common command/push/pull bus is used for resource sharing, then device complexity is reduced, but memory contention and access conflicts increase
Solution Approach 1:
The CPP bus implements dynamic arbitration and timing control where microengines can issue commands and data transfers are scheduled based on current system state. The bus controller dynamically manages access rights, prioritizing critical operations and handling conflicts through intelligent scheduling, thereby maintaining system reliability while using a shared bus structure.
Data Source
AI summary
A transactional memory (TM) receives a lookup command across a bus from a processor. Only final result values are stored in memory. The command includes a base address, a starting bit position, and mask size. In response to the lookup command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV and the base address are used to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a result location value (RLV) generated from the portion of the IV. A word selector circuit and arithmetic circuits are used to generate the memory address and RLV. The TM sends the selected RV to the processor.