Wireless Transceiver Reference Clock Switching for Low Phase Noise
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Solution Overview
Problem
Electronic devices with wireless communications capabilities face issues due to excessive phase noise in clock signals, which can degrade transmission and reception performance.
Innovation Solution
The implementation of a transceiver with switchable high side injection (HSI) and low side injection (LSI) modes, utilizing a reference oscillator, reference phase-locked loop (PLL), intermediate frequency PLL, and radio-frequency PLL, along with a switch and optional frequency divider, to generate and correlate clock signals, minimizing phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are used for signal conversion in mixers, then signal conversion between baseband and radio frequencies is achieved, but excessive phase noise is injected into the signal
Solution Approach 1:
The clock signal generation is segmented into multiple independent sources: a reference oscillator and two separate PLLs (first PLL for IF clock, second PLL for RF clock). This segmentation allows independent optimization and control of each clock source to minimize phase noise injection during signal conversion.
Solution Approach 2:
The invention changes the frequency parameters of clock signals dynamically. The first clock signal operates at an intermediate frequency while the second clock signal operates at radio frequency. By adjusting these frequency parameters and their correlation relationships, the system optimizes phase noise performance for different operating conditions.
2Device complexity
If a single reference signal is used for both first and second clock signals, then device complexity is reduced, but phase noise cancellation effectiveness is compromised
Solution Approach 1:
The system dynamically switches between two operational modes: HSI mode where both clock signals are derived from the reference PLL output (correlated), and LSI mode where they are derived from different sources (decorrelated). This dynamic adaptability allows the system to optimize phase noise performance while managing complexity based on operating conditions.
Solution Approach 2:
A switch is introduced as an intermediary component that selectively connects the reference oscillator or reference PLL output to the second PLL input. This intermediary enables flexible reconfiguration of the clock signal generation path, allowing the system to choose between correlated and decorrelated clock signal modes as needed.
3Productivity
If high side injection mode is used for mixing, then certain frequency conversion advantages are achieved, but phase noise is injected into the signal
Solution Approach 1:
The invention inverts the conventional approach by using LSI mode instead of HSI mode in certain conditions. By switching between HSI and LSI modes, the system can exploit the different phase noise characteristics of each mode to minimize overall phase noise injection while maintaining signal conversion efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively cancels out phase noise injected by mixers, enhancing signal conversion efficiency and reducing interference in wireless communications.
Implementation Method 1
A reference oscillator may be provided. The reference phase-locked loop (PLL) may have an input coupled to an output of the reference oscillator
Implementation Method 2
The reference PLL may generate a second reference signal by upconverting the first reference signal
Implementation Method 3
The radio frequency PLL may generate the second clock signal by upconverting the second reference signal
Implementation Method 4
The intermediate frequency PLL may generate the first clock signal by upconverting the second reference signal
Implementation Method 5
The first mixer may convert a signal on the signal path between a baseband frequency and an intermediate frequency using a first clock signal
Implementation Method 6
The second mixer may convert the signal between the intermediate frequency and a radio frequency using a second clock signal
Data Source
AI summary
An electronic device may include wireless circuitry with first and second mixers on a signal path for converting a signal using first and second clock signals via high side injection (HSI) or low side injection (LSI). A first phase-locked loop (PLL) may generate the first clock signal and a second PLL may generate the second clock signal. A switch may couple the first PLL to a reference oscillator when LSI is used and may couple the first PLL to a third PLL when HSI is used. The third PLL may generate a second reference signal based on a first reference signal from the reference oscillator. The second PLL may generate the second clock signal based on the output of the third PLL. This may serve to may minimize phase noise even as the mixers switch between HSI and LSI.