Transistor Array Substrate Feed Interconnection Resistance Reduction
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Solution Overview
Problem
Conventional organic electroluminescent display panels with active matrix driving types face issues with voltage drop and signal delay due to high resistance in interconnections, which affect the performance and efficiency of light-emitting elements.
Innovation Solution
A transistor array substrate with a matrix arrangement of driving transistors, signal lines, supply lines, and feed interconnections, where the feed interconnections are formed separately and thickened to reduce resistance, and the supply lines are formed on signal lines during electroplating to grow feed interconnections, thereby minimizing voltage drop and signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the interconnection is formed from the conductive thin film with the same thickness as the thin-film transistor, then the manufacturing process is simplified, but the resistance of the interconnection is high causing voltage drop and signal delay
Solution Approach 1:
The interconnection structure is segmented into multiple layers: a first conductive layer (thin-film transistor electrode) and a second conductive layer (additional conductive film) that is selectively formed only in the interconnection region. This segmentation allows the interconnection to have different properties than the transistor electrode, achieving low resistance without affecting transistor performance.
Solution Approach 2:
The patent applies local quality by forming the second conductive layer specifically in the interconnection region while leaving the transistor electrode region unchanged. This localized modification reduces interconnection resistance without altering the thin-film transistor characteristics, solving the contradiction between manufacturing simplicity and interconnection performance.
2Reliability
If the metal layer is made thick or patterned wide to reduce interconnection resistance, then voltage drop and signal delay are suppressed, but the overlap area increases generating parasitic capacitance that retards current flow
Solution Approach 1:
Instead of increasing the width (horizontal dimension) of the interconnection to reduce resistance, the patent adds a vertical dimension by forming a second conductive layer on top of the first conductive layer. This dimensional transition reduces resistance through increased cross-sectional area without increasing the horizontal overlap area, thus avoiding parasitic capacitance.
3Reliability
If the gate electrode is made thick to lower resistance, then interconnection performance improves, but a thick planarization film is required which causes large changes in transistor characteristic
Solution Approach 1:
The patent extracts the interconnection function from the gate electrode structure. Instead of making the gate electrode thick to reduce interconnection resistance, the interconnection is formed as a separate second conductive layer that is selectively applied only where needed, leaving the gate electrode thin and maintaining transistor characteristic stability.
4Reliability
If the source and drain are formed thick to reduce resistance, then interconnection performance improves, but etching accuracy degrades which adversely affects transistor characteristic
Solution Approach 1:
The patent performs preliminary action by forming the second conductive layer selectively in the interconnection region before final transistor fabrication steps. This allows the interconnection to have low resistance while the source and drain regions maintain their original thin structure, preserving etching accuracy and transistor characteristic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses voltage drop and signal delay, ensuring efficient current supply to light-emitting elements and maintaining high display performance by reducing the resistance of feed interconnections.
Implementation Method 1
supply lines are formed on signal lines during electroplating to grow feed interconnections
Data Source
AI summary
A transistor array substrate includes a plurality of driving transistors which are arrayed in a matrix on a substrate. The driving transistor has a gate, a source, a drain, and a gate insulating film inserted between the gate, and the source and drain. A plurality of signal lines are patterned together with the gates of the driving transistors and arrayed to run in a predetermined direction on the substrate. A plurality of supply lines are patterned together with the sources and drains of the driving transistors and arrayed to cross the signal lines via the gate insulating film. The supply line is electrically connected to one of the source and the drain of the driving transistor. A plurality of feed interconnections are formed on the supply lines along the supply lines, respectively.