Dual-Sided Transistor Contacts With Doped Backside Interfacial Layer
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Solution Overview
Problem
High contact resistances on the backside contacts to the source/drain (S/D) region in transistor devices lead to reduced drive currents, limiting performance improvement in dual-sided metallization schemes.
Innovation Solution
The introduction of an interfacial layer with low resistivity material, such as silicon or silicon and carbon, between the bottom surface of the S/D region and the backside contact, which has a high active dopant concentration, is used to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dual-sided metallization scheme is used to contact S/D regions from top and bottom surfaces, then capacitance between metal lines is decreased, but contact resistance increases due to poor or non-ohmic contact between backside metal and S/D regions
Solution Approach 1:
An interfacial layer is introduced between the backside metal contact and the source/drain region to serve as an intermediary that improves electrical contact. This layer, composed of materials such as silicon, silicon-germanium, or silicon-carbon with high doping concentrations, facilitates ohmic contact and reduces contact resistance, thereby resolving the reliability issue while maintaining the low capacitance benefit of dual-sided metallization
Solution Approach 2:
The electrical properties of the contact interface are improved by changing the doping concentration parameter of the interfacial layer. By implementing high doping concentrations (e.g., 1E19 to 1E21 atoms/cm³) in the interfacial layer, the contact resistance is significantly reduced, transforming the poor non-ohmic contact into a reliable low-resistance connection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The interfacial layer significantly decreases contact resistance, enhancing drive current and overall transistor performance by ensuring efficient electrical connectivity between the S/D regions and the backside contact.
Implementation Method 1
The interfacial layer comprises a low resistivity material and has a high active dopant concentration
Data Source
AI summary
Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.