Power Transistor Driver Circuit Reducing Voltage Spikes

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Solution Overview

Problem

Switching converters face challenges in reducing voltage spikes at the switching node due to parasitic inductance, leading to increased costs and potential EMI, while high load drivability is required for fast transistor switching.

Innovation Solution

A driver circuit comprising two transistors, where one transistor is turned on and off by a first driving signal, and the other is turned on and off by a second driving signal, with specific timing to manage the switching voltage and minimize voltage spikes, utilizing a control signal generating circuit to manage the switching process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If driver with high load drivability is used to fast turn on and off power transistor, then switching loss is reduced, but high SW voltage spikes are created due to parasitic elements

Engineering Contradiction:
Improveswitching lossVSAvoidvoltage spikes
Core Design Contradiction:
Loss of energyVSObject-generated harmful factors

Solution Approach 1:

The driver circuit performs preliminary action by pre-charging the gate terminal before the power transistor switches on, and by proactively managing the gate voltage during switching transitions. The circuit prepares the gate charge in advance and controls the discharge timing to prevent voltage spikes before they occur, rather than reacting after the spikes are generated.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The driver circuit dynamically adjusts the gate voltage waveform by controlling the charging and discharging rates of the gate terminal. The circuit changes the driving characteristics in real-time during switching transitions, optimizing the gate voltage profile to achieve fast switching while minimizing voltage spikes through dynamic control of charge transfer rates.

Inventive Principle:
Principle #15Dynamics

2Reliability

If high voltage spikes are generated at switching node, then breakdown voltage of power transistor must be increased, but cost increases

Engineering Contradiction:
Improvebreakdown voltage withstand capabilityVSAvoidcost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The driver circuit converts the potentially harmful effect of gate charge discharge into a beneficial pre-charging action. By controlling the discharge of gate charge through a resistor before the switching event, the circuit transforms what would be a source of voltage spikes into a mechanism that prepares the gate for optimal switching, thereby reducing spikes without requiring higher breakdown voltage transistors.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Speed

If high voltage spikes occur at switching node, then EMI is caused to nearby circuit, but switching speed must be maintained

Engineering Contradiction:
Improveswitching speedVSAvoidEMI
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The driver circuit introduces an intermediary element (resistor) between the gate charge source and the gate terminal. This intermediary component controls the rate of charge transfer, acting as a buffer that smooths the switching transitions. The resistor mediates the interaction between the fast switching requirement and the EMI reduction need by controlling the dv/dt of the gate voltage while maintaining overall switching speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10840795B1Power transistor driver with reduced spikes for switching converters
Publication Date: 2020.11.17 MONOLITHIC POWER SYSTEMS INC
  • US10840795B1 patent drawing
  • US10840795B1 patent drawing
  • US10840795B1 patent drawing

AI summary

A driver for driving a power transistor, the driver having: a first transistor, and a second transistor; wherein (1) when the first transistor is turned on, the second transistor is simultaneously turned on, and wherein after the second transistor remains on for a first time period, the second transistor is turned off for a second time period during when a switching voltage at a second terminal of the power transistor is rising, and the second transistor is turned on after the second time period is over; and (2) when the first transistor is turned off, the second transistor is simultaneously turned off.