Transistor Gate Foot Formation for Channel Width Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current techniques for manufacturing MOSFET transistors face challenges in precisely controlling the dimensions of the silicon channel, particularly in reducing the width of the channel between the source and drain, which affects the electrical performance and integration density of transistors.
Innovation Solution
A method involving the formation of a gate foot with precisely controlled physical parameters, where a dielectric layer is used to form spacers that do not cover the gate foot, allowing for partial removal of the underlying semiconductor material to create a gate foot and peripheral portion, enabling conformal deposition and subsequent etching to define the channel with precision, thereby reducing the channel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional self-alignment technique with gate as mask is used, then source and drain zones are formed, but the channel width cannot be precisely controlled and reduced
Solution Approach 1:
The gate structure is segmented into two distinct parts: the main gate body and the protruding gate foot. This segmentation allows the gate foot to define the channel width independently from the main gate, enabling precise control of channel dimensions while maintaining the self-alignment benefit of using the gate as a mask for source/drain formation.
Solution Approach 2:
The gate foot protrudes into the underlying semiconductor layer in the vertical dimension, creating a three-dimensional structure. This dimensional change allows the channel width to be defined by the gate foot's projection into the substrate rather than by lateral dimensions alone, enabling more precise width control.
2Manufacturing precision
If spacers are formed to protect gate zones during source/drain formation, then gate is protected, but channel width reduction is limited
Solution Approach 1:
The gate foot is formed in advance before the spacer deposition step. By pre-forming the gate foot that protrudes into the semiconductor layer, the subsequent spacer formation process can use this pre-existing structure as a template, simplifying the overall manufacturing process while achieving precise channel width definition.
Solution Approach 2:
The gate foot structure serves dual functions: it acts as both the gate electrode and the template for defining channel width. The gate foot's own geometry self-defines the channel dimensions, eliminating the need for separate complex alignment processes and making the manufacturing easier.
3Reliability
If original layer thickness is reduced for fully depleted channel, then channel is fully devoid of carriers, but control of channel dimensions becomes more difficult
Solution Approach 1:
The gate foot is designed with specific local dimensions that differ from the main gate body. The gate foot's width and projection depth into the semiconductor layer are precisely controlled to define the channel width, while the original layer thickness is independently optimized for full depletion. This local differentiation allows simultaneous achievement of full depletion and precise dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise control of the transistor channel dimensions, enabling dopants to be brought closer to the silicon channel, reducing the channel width, and improving the electrical performance and integration density of transistors.
Implementation Method 1
a step of formation of a dielectric layer in such a way as to form spacers that cover at least partially said first and second flanks of the gate in such a way as to not cover at least partially said gate foot
Implementation Method 2
it was then necessary to increase their section. This is obtained by selective epitaxy of the source/drain zones 1100, 1200
Implementation Method 3
The formation of the source and drain zone 1100, 1200 is typically carried out by ionic implantation of dopants in the zones 1100, 1200, with the gate 1000 serving as a mask
Data Source
AI summary
There is provided a method for manufacturing a transistor including a gate above an underlying layer of a semiconductor material and including at least one first flank and one second flank, a gate foot formed in the underlying layer, a peripheral portion of the underlying layer surrounding the gate foot, and spacers covering at least partially the first and second flanks so as to not cover the gate foot; the method including forming the underlying layer by partially removing the semiconductor material around the gate to form the gate foot and the peripheral portion; then forming a dielectric layer for forming spacers by a deposition to cover both the first and second flanks, the gate foot, and an upper surface of the peripheral portion; and then partially removing the dielectric layer so as to expose the upper surface and so as to not expose the first and second flanks.