Transistor Gate Stack Height Reduction via Segmentation
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Solution Overview
Problem
The performance of nanometer-scale transistors is hindered by parasitic capacitance due to the height of the gate stack, which limits the reduction of the gate stack height and affects the threshold voltage adjustment, making it challenging to improve transistor performance.
Innovation Solution
A transistor design that incorporates a back gate for threshold voltage adjustment, with a gate stack height lower than the spacer height, reducing parasitic capacitance and utilizing a back gate contact formed by epitaxy to simplify manufacturing and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate stack height is increased to serve as a barrier layer in the manufacturing process, then the manufacturing process can proceed sequentially with proper barrier function, but the parasitic capacitance between gate stack and electric contact increases, degrading transistor performance
Solution Approach 1:
The gate stack is segmented into two functional parts: the active gate stack (gate electrode + gate dielectric) with reduced height for low parasitic capacitance, and a separate barrier layer with appropriate height for manufacturing process functionality. This segmentation allows each part to optimize its height independently, resolving the contradiction between manufacturing requirements and performance requirements.
Solution Approach 2:
The barrier layer function is extracted from the gate stack structure. Instead of relying on the gate stack to serve both as the active gate and barrier layer, the barrier layer function is separated into a distinct structural element. This extraction allows the gate stack height to be reduced for performance while the barrier layer maintains its height for manufacturing process requirements.
2Object-affected harmful factors
If the gate stack height is reduced to improve transistor performance by reducing parasitic capacitance, then the parasitic capacitance decreases, but the gate stack can no longer function as a barrier layer in the manufacturing process
Solution Approach 1:
The gate stack is segmented into two functional parts: the active gate stack (gate electrode + gate dielectric) with reduced height for low parasitic capacitance, and a separate barrier layer with appropriate height for manufacturing process functionality. This segmentation allows each part to optimize its height independently, resolving the contradiction between manufacturing requirements and performance requirements.
Solution Approach 2:
The barrier layer function is extracted from the gate stack structure. Instead of relying on the gate stack to serve both as the active gate and barrier layer, the barrier layer function is separated into a distinct structural element. This extraction allows the gate stack height to be reduced for performance while the barrier layer maintains its height for manufacturing process requirements.
3Adaptability or versatility
If the threshold voltage is adjusted by changing the work function of the gate stack, then the threshold voltage can be tuned, but the material composition and height of the gate stack are constrained, limiting design flexibility
Solution Approach 1:
The back gate serves as an intermediary mechanism for threshold voltage adjustment. Instead of directly modifying the gate stack material or dimensions, the back gate provides indirect control of the threshold voltage through electric field modulation. This intermediary approach decouples the threshold voltage adjustment from the gate stack structure, providing design flexibility without adding complexity to the gate stack itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances transistor performance by reducing parasitic capacitance and allowing for effective threshold voltage adjustment without additional protective layers, simplifying the manufacturing process and reducing costs.
Implementation Method 1
a back gate contact formed on a portion of the back gate, wherein the back gate contact comprises a part raised from the surface of the back gate
Data Source
AI summary
The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.