Transistor Modeling Using Actual Geometric Shapes
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Solution Overview
Problem
Conventional EDA tools fail to accurately account for manufacturing effects during IC fabrication, leading to inaccuracies in electrical parameter extraction due to deviations in transistor shapes caused by systematic and random variations, which are critical in modern designs with smaller feature sizes and tighter component spacing.
Innovation Solution
A method and system that model the actual shape of transistors based on both systematic and random variations, using a mathematical model of the lithography process to determine expected random variations, allowing for accurate extraction of electrical parameters by analyzing the expected printed geometries rather than idealized models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional EDA tools use idealized geometric models for transistors, then the extraction process is simple and fast, but the accuracy of electrical parameter extraction deteriorates due to manufacturing variations
Solution Approach 1:
The patent changes the geometric parameters of transistor models from idealized shapes to physically accurate shapes that incorporate manufacturing variations. The system extracts actual geometric parameters (width, length, area) from fabricated transistor images and uses these real measurements to update the component models, thereby improving extraction accuracy while maintaining manageable complexity through automated parameter extraction and model updating processes.
2Productivity
If the feature size is reduced for modern IC designs, then the integration density increases, but the manufacturing precision deteriorates due to increased sensitivity to process variations
Solution Approach 1:
The patent implements a feedback mechanism where fabricated transistor images are analyzed to extract actual geometric parameters, and these measured values are fed back to update the component models. This closed-loop approach allows the system to continuously improve its accuracy in representing actual transistor geometries, compensating for manufacturing variations and maintaining reliable extraction even as feature sizes are reduced for higher integration density.
3Reliability
If systematic and random variations are accounted for in transistor modeling, then the accuracy of electrical characteristics improves, but the extraction process becomes more complex and time-consuming
Solution Approach 1:
The patent performs preliminary actions by pre-establishing frameworks for capturing and processing manufacturing variations. The system prepares templates and methodologies for extracting geometric parameters before actual analysis is needed, enabling efficient processing during extraction. This preliminary preparation allows the system to handle complex variations systematically without significantly increasing real-time extraction time.
Data Source
AI summary
An improved method, system, and computer program product is disclosed for predicting the geometric model of transistors once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for modeling transistors since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The expected geometric shape includes systematic variations, which can be determined based on the layout, and the expected random variations, which can be determined based on the lithographic process.