Transistor Stress Testing With Constant-Current Gate Feedback
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Solution Overview
Problem
The challenge with existing stress testing of semiconductor devices, particularly Gallium Nitride (GaN) high electron mobility transistors, is that the ON resistance increases with temperature, leading to a prolonged testing duration and increased costs due to the need for maintaining high voltage and temperature for extended periods.
Innovation Solution
The apparatus and method involve adjusting the voltage at the control terminal of the transistor to maintain a constant current through the transistor during stress testing, using an amplifier to compensate for changes in ON resistance, thereby reducing the testing duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage and temperature are maintained for extended periods to stress test transistors, then reliability testing is improved, but testing duration increases and costs increase
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage applied to the transistor during stress testing. Instead of maintaining constant high voltage, the system monitors transistor characteristics and modifies voltage parameters in real-time to maintain constant current flow. This approach achieves comprehensive reliability testing while reducing the required testing duration from extended periods to shorter intervals, directly resolving the contradiction between thorough reliability assessment and testing time efficiency
2Reliability
If high voltage and temperature are maintained for extended periods to stress test transistors, then reliability testing is improved, but testing costs increase
Solution Approach 1:
The system dynamically changes voltage parameters during testing based on real-time transistor performance monitoring. By adjusting voltage to maintain constant current rather than sustaining maximum voltage throughout the test, the method reduces energy consumption during stress testing while still achieving comprehensive reliability validation, thereby lowering testing costs without compromising reliability assessment quality
3Loss of time
If voltage is adjusted to maintain constant current during stress testing, then testing duration is reduced, but device complexity increases
Solution Approach 1:
The patent implements feedback control by continuously monitoring transistor current during stress testing and using this information to adjust the applied voltage. The system measures actual current flow and compares it against the target constant current level, then modifies voltage parameters accordingly to maintain the desired current. This feedback mechanism enables accelerated testing with reduced duration while managing device complexity through automated control rather than manual intervention
Solution Approach 2:
The patent replaces manual testing procedures with an automated electronic control system that uses feedback loops and electronic signal processing to maintain constant current. This substitution of mechanical/manual operations with electronic automation reduces testing duration and manages complexity through integrated electronic control circuits rather than complex mechanical adjustment mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for faster stress testing by maintaining a constant current, thereby reducing testing time from hours to minutes, lowering costs and improving chip production efficiency.
Implementation Method 1
the ON resistance increases with temperature, leading to a prolonged testing duration... adjusting the voltage at the control terminal of the transistor to maintain a constant current through the transistor during stress testing, using an amplifier to compensate for changes in ON resistance
Data Source
AI summary
A first voltage supply is coupled to a first terminal of a test transistor. A first terminal of a probe circuit is coupled to the first terminal of the test transistor. A second terminal of the probe circuit is coupled to a second terminal of the test transistor. A third terminal of the probe circuit is coupled to a control terminal of the test transistor. A first terminal of the first resistor is coupled to the second terminal of the test transistor. A second terminal of the first resistor is coupled to a second voltage supply. A first input terminal of an amplifier is coupled to a third voltage supply. A second input terminal of an amplifier is coupled to the first terminal of the first resistor. An output terminal of an amplifier is coupled to the control terminal of the test transistor.