Transparent Latch Cycle Boundary Adjustment for Power Reduction
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Solution Overview
Problem
Existing digital integrated circuits face challenges in optimizing timing adjustments across transparent latches, which limits power reduction opportunities during static timing analysis, as the cycle boundary selection primarily balances timing slack without considering power reduction potential.
Innovation Solution
A method that adjusts the cycle boundary of transparent latches based on input and output potential power savings, shifting timing slack from the side with lower power savings potential to the side with higher potential, using a processor to determine the optimal weighting factor and ensure the adjusted cycle boundary remains within the transparent interval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cycle boundary is selected to balance timing slack, then timing correctness is ensured, but power reduction opportunities are limited
Solution Approach 1:
The patent changes the cycle boundary parameter from a fixed timing-based selection to a dynamic selection that incorporates power savings potential. By adjusting the cycle boundary position based on both timing slack and power reduction opportunities, the system achieves better power efficiency while maintaining timing correctness. This is accomplished by modifying the objective function in static timing analysis to include power metrics alongside timing metrics.
2Use of energy by moving object
If timing slack is increased on one side of the transparent latch, then power savings potential increases on that side, but timing slack on the other side decreases
Solution Approach 1:
The patent applies asymmetry by allowing unequal distribution of timing slack between the input and output sides of the transparent latch. Instead of forcing symmetric timing margins, the system strategically allocates timing slack to the side with higher power savings potential, accepting asymmetric timing margins that optimize overall power consumption while meeting timing requirements.
Solution Approach 2:
The patent introduces dynamic adjustment of the cycle boundary position based on power savings potential analysis. The system dynamically determines the optimal cycle boundary location that maximizes power reduction opportunities, allowing the timing slack distribution to adapt to the specific power characteristics of the circuit being analyzed.
Data Source
AI summary
A method of implementing timing adjustments across a transparent latch of an integrated circuit, a system, and a computer program product are described. The method includes obtaining initial input timing slack and input potential power savings at an input and an initial output timing slack and output potential power savings at an output of the transparent latch. The method also includes adjusting a cycle boundary of the transparent latch to obtain a new input timing slack at the input and a new output timing slack at the output of the transparent latch, wherein the new input timing slack is greater than the initial input timing slack based on the input potential power savings being greater than the output potential power savings and the new output timing slack is greater than the initial output timing slack based on the output potential power savings being greater than the input potential power savings.