Transpose Circuit for Matrix Element Reordering in DRAM
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Solution Overview
Problem
Matrix operations in computer systems face inefficiencies due to the storage sequence of matrix elements in DRAM, leading to increased power consumption and performance degradation, as non-consecutive addresses require multiple read commands, whereas consecutive addresses can utilize burst read commands for improved access.
Innovation Solution
A matrix device with a transpose circuit that rearranges matrix elements from a native matrix into either row-major or column-major format, allowing the memory to store elements in a configuration that matches access calculation characteristics, thereby optimizing memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If matrix elements are stored in DRAM in column-major manner after previous matrix operation, then the storage sequence matches column-major access patterns, but the next matrix operation requiring row-major access must use multiple discrete read commands instead of burst read, increasing power consumption and reducing performance
Solution Approach 1:
The patent applies preliminary action by transposing the matrix elements from column-major order to row-major order before storing them in DRAM. This pre-transposition ensures that when the next matrix operation requires row-major access, the elements are already arranged in the correct sequence, enabling burst read commands and avoiding multiple discrete reads. The transpose circuit performs this reordering operation in advance, so the memory storage configuration is optimized for the anticipated access pattern of the subsequent operation.
2Productivity
If matrix elements are stored in non-consecutive addresses in DRAM, then the storage structure reflects the generating sequence of previous operation, but multiple read commands are required instead of single burst read, increasing access time and reducing efficiency
Solution Approach 1:
The transpose circuit performs preliminary reordering of matrix elements before they are stored in DRAM. By converting elements from column-major sequence to row-major sequence in advance, the circuit ensures that elements requiring simultaneous access are positioned at consecutive memory addresses. This preliminary arrangement eliminates the need for multiple discrete read commands and enables efficient burst reads, significantly reducing memory access time for subsequent operations.
3Ease of operation
If matrix elements are accessed from non-consecutive addresses in DRAM, then the access pattern matches the native matrix structure, but multiple read commands increase the number of memory accesses and reduce overall system performance
Solution Approach 1:
The patent employs preliminary action through a transpose circuit that reorders matrix elements from column-major to row-major sequence before storage. This pre-processing step ensures that elements needed for the next matrix operation are already arranged in consecutive memory addresses matching the required access pattern. As a result, the memory access operation becomes simple and efficient, requiring only a single burst read command rather than multiple discrete reads, thereby improving both ease of operation and overall throughput.
Data Source
AI summary
The present disclosure provides a matrix device and an operation method thereof. The matrix device includes a transpose circuit and a memory. The transpose circuit is configured to receive a first element string representing a native matrix from a matrix source, wherein all elements in the native matrix are arranged in the first element string in one of a “row-major manner” and a “column-major manner”. The transpose circuit transposes the first element string into a second element string, wherein the second element string is equivalent to an element string in which all elements of the native matrix are arranged in another one of the “row-major manner” and the “column-major manner”. The memory is coupled to the transpose circuit to receive the second element string.


