Transpose Accessing SRAM With Local I/O Circuits
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Solution Overview
Problem
Conventional SRAM designs for transpose accessing are not area-efficient and require excessive power and time consumption when accessing data by column, and previous modifications to support column access often compromise stability and yield, leading to discarded designs.
Innovation Solution
A memory device with a hierarchical bit-line structure using local I/O circuits to guide local bit-lines to global bit-lines in different directions, allowing for efficient row and column access modes without modifying the traditional memory cell design, thereby achieving energy-saving, time-saving, and area-efficient characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SRAM designs are used for transpose accessing, then column access can be implemented, but power consumption and time consumption increase excessively
Solution Approach 1:
The memory system is segmented into multiple banks, each with its own local I/O circuits. This segmentation allows column access to be performed locally within each bank rather than requiring global access across the entire memory array, reducing power consumption and access time.
Solution Approach 2:
Local I/O circuits are introduced as intermediary components between the memory cells and global bit-lines. These local I/O circuits enable efficient column access by providing a local access path, reducing the need to activate entire global bit-line structures and thereby reducing power consumption.
2Productivity
If previous arts modified memory cell design for transpose accessing, then column access efficiency is improved, but stability and yield are affected
Solution Approach 1:
The transpose access functionality is extracted from the memory cell design itself and implemented separately through local I/O circuits and control logic. This extraction allows the memory cells to remain unchanged and reliable, while column access efficiency is improved through the added local access paths.
Solution Approach 2:
The local I/O circuits provide multi-functionality by supporting both row access and column access operations. This universal access interface enables efficient column access without requiring modifications to the memory cell structure, thereby maintaining stability and yield.
3Ease of manufacture
If conventional memory architecture is used, then traditional memory cell design is maintained, but area efficiency and access speed are compromised
Solution Approach 1:
The memory access architecture is extended from a single global access dimension to multiple dimensions by introducing local I/O circuits and hierarchical bit-line structures. This dimensional expansion enables simultaneous row and column access paths, improving access speed while maintaining traditional memory cell design.
4Adaptability or versatility
If all rows are read to obtain column data, then column access is possible, but time consumption and power consumption increase
Solution Approach 1:
Local I/O circuits are pre-configured and positioned at each memory bank to enable direct column access. This preliminary arrangement of local access paths eliminates the need to read all rows when column data is required, significantly reducing access time and power consumption.
Data Source
AI summary
A transpose accessing memory device is provided, the global word-lines configured to be selected as horizontal word-lines in a row access mode in that at least one row of the memory array is selected to be access, and the corresponding local I/O circuit is configured to guide signals of the local bit-lines coupled to the selected SRAM memory cells to the corresponding horizontal global bit-lines in response to select signals from the global word-lines, and the global word-lines configured to be selected as vertical word-lines in a column access mode in that at least one column of the memory array is selected to be access, and the corresponding local I/O circuit is configured to guide signals of the local bit-lines coupled to the selected SRAM memory cells to the corresponding vertical global bit-lines in response to select signals from the global word-lines.