Trapezoidal Floating Gate with Partial IPD for NAND Flash Scaling
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Solution Overview
Problem
Conventional NAND-type flash memories face challenges in further scaling of memory cells due to difficulties in forming thick inter poly dielectric (IPD) films, which are necessary for maintaining capacitance ratios and preventing leakage, especially as design rules approach 30 nm, leading to interference between adjacent floating gates and reduced operational efficiency.
Innovation Solution
The proposed solution involves a trapezoidal floating gate structure with a thicker IPD film than the tunnel film, where the IPD film is only formed on the upper portion of the floating gate, eliminating the need for three-dimensional IPD films and high permittivity materials, allowing for stable electron injection and emission without leakage, and enabling scaling in both horizontal and vertical directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory cell is scaled down to maintain capacitance ratios and prevent leakage, then the operational reliability is improved, but the manufacturing difficulty increases due to interference between adjacent floating gates
Solution Approach 1:
The IPD film formation is segmented to be applied only to the upper portion of the floating gate rather than the entire structure. This selective segmentation reduces interference between adjacent floating gates while maintaining necessary capacitance ratios, thereby improving manufacturability at scaled dimensions without compromising operational reliability
Solution Approach 2:
The patent applies different IPD film thicknesses to different regions: a thicker IPD film on the upper portion of the floating gate for capacitance maintenance, and no IPD film on side portions to prevent interference with adjacent cells. This local quality differentiation resolves the contradiction between reliability and manufacturing ease
2Reliability
If a thick IPD film is formed on the entire floating gate, then the capacitance ratio is maintained, but the leakage between adjacent cells increases
Solution Approach 1:
The patent implements local quality by forming the IPD film only on the upper portion of the floating gate where it is needed for capacitance ratio maintenance, while deliberately excluding side portions where it would cause leakage. This spatial differentiation of IPD film presence simultaneously achieves both objectives
Solution Approach 2:
The IPD film coverage is segmented into distinct regions: covered upper portion for capacitance function and uncovered side portions for leakage prevention. This segmentation strategy resolves the contradiction between maintaining capacitance ratio and preventing inter-cell leakage
3Reliability
If three-dimensional IPD films or high permittivity materials are used, then the capacitance ratio is improved, but the device complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for complex three-dimensional IPD film structures and high permittivity materials by using a simplified planar IPD film configuration on the upper portion of the floating gate. This extraction of unnecessary complexity maintains capacitance ratios while significantly reducing device complexity
Solution Approach 2:
The patent changes the structural parameter of IPD film from three-dimensional to planar, and modifies the material parameter by eliminating the need for high permittivity materials. These parameter changes achieve capacitance ratio maintenance through geometric optimization rather than material complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains sufficient capacitance ratios without the need for three-dimensional IPD films or high permittivity materials, allowing for stable operation, reduced leakage, and the ability to store multi-level information, while suppressing the short channel effect and enhancing operational speed.
Implementation Method 1
maintaining capacitance ratios and preventing leakage
Implementation Method 2
stable electron injection and emission without leakage
Data Source
AI summary
According to one embodiment, a non-volatile memory includes a first non-volatile memory cell and a first selected transistor. A first cell block is formed by connecting a plurality of first non-volatile memory cells in series. An area S1 of the first insulating film at which the first floating gate is in contact with the first silicon channel is larger than an area S2 of the second insulating film at which the first floating gate is in contact with the first gate electrode.