Trapping Dislocations in High-Mobility FinFET Fins Below Isolation Layer
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Solution Overview
Problem
Conventional methods for forming high-mobility fins in finFET devices on silicon germanium substrates result in lattice dislocations that adversely affect electron/hole mobility and device performance, and require tall isolation layers that increase device thickness and complicate fabrication.
Innovation Solution
A method of forming a high-mobility fin by trapping dislocations in a recess below the isolation layer on a silicon-on-insulator (SOI) substrate, allowing the fin to grow from the recess and extending above the isolation layer, thereby reducing the need for a tall isolation layer and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional methods are used to form high-mobility fins on silicon germanium substrates, then electron/hole mobility is improved, but lattice dislocations occur that adversely affect device performance
Solution Approach 1:
The fin structure is segmented into two distinct regions: a high-mobility germanium-containing semiconductor fin region and a separate isolation layer region. This segmentation allows the fin to achieve high electron/hole mobility in its active region while isolating potential dislocation effects in the isolation layer, thereby resolving the contradiction between improved mobility and maintained device performance
Solution Approach 2:
An isolation layer is introduced as an intermediary structure between the high-mobility fin and the substrate. This isolation layer acts as a mediator that prevents lattice dislocations from propagating into the fin region, allowing the fin to maintain high electron/hole mobility without the adverse effects of dislocations on device performance
2Reliability
If tall isolation layers are used to prevent dislocation effects, then device performance is maintained, but device thickness increases and fabrication is complicated
Solution Approach 1:
The isolation layer is engineered with specific compositional parameters (germanium content gradient) and thickness parameters that optimize its ability to prevent dislocation effects. By carefully controlling the germanium content to increase from bottom to top and selecting an appropriate thickness, the isolation layer maintains device performance while minimizing device thickness and avoiding the need for tall isolation structures
3Speed
If germanium-on-insulator (GOI) substrates are used to form finFET devices, then high mobility is achieved, but substrate cost increases significantly
Solution Approach 1:
The invention uses a composite material structure consisting of a silicon substrate with a silicon-germanium alloy fin and a silicon-germanium isolation layer. This composite structure combines the low cost of silicon substrates with the high mobility benefits of germanium-containing materials, achieving high electron mobility without the significantly higher cost of complete GOI substrates
Solution Approach 2:
Germanium is applied locally only where high mobility is needed (in the fin region and isolation layer) rather than throughout the entire substrate. This local quality approach maintains the cost-effectiveness of silicon substrates while achieving high electron mobility in the critical active regions of the device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of thinner, more affordable high-mobility fins with improved electron/hole mobility and reduced device thickness, allowing for tighter fin pitch and simpler fabrication without the complications of high-aspect ratio techniques.
Implementation Method 1
epitaxially growing a material having high electron mobility properties in the recess to form a high-mobility fin
Data Source
AI summary
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.