Trench Capacitor Top Plate Void Elimination
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Solution Overview
Problem
Integrated trench capacitors face issues with silicon undercutting during deep trench etching, resulting in smaller silicon nitride openings and voids/seams at the top plate surface, which increase contact resistance and can lead to open circuits, reducing capacitance density and increasing variation due to random void-induced open circuits.
Innovation Solution
Incorporating a silicon nitride etch back process to enlarge the silicon nitride opening area to match or exceed the silicon opening area below, effectively eliminating voids in the top plate and ensuring reliable contact, by using a method that includes forming a patterned photoresist layer, etching deep trenches, lining with oxide, and performing a wet nitride etch to ensure adequate space for contact landing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep trench etching is performed to form integrated trench capacitors, then capacitance density is improved, but silicon undercutting occurs causing smaller silicon nitride openings and voids at the top plate surface
Solution Approach 1:
A silicon nitride pull-back etch step is performed before depositing the top plate material. This preliminary action enlarges the silicon nitride opening area to match or exceed the silicon opening area below, preventing void formation when the top plate material is subsequently deposited and ensuring a uniform top plate surface.
2Manufacturing precision
If conventional CMP is used to define the top plate, then planarization is achieved, but slurry particles are trapped in voids creating defects
Solution Approach 1:
The silicon nitride pull-back etch is performed as a preliminary step before top plate deposition, ensuring the opening is sufficiently large to prevent void formation. This eliminates the root cause of slurry particle trapping, allowing CMP to proceed without creating defects from particle entrapment in voids.
3Reliability
If voids are present at the top plate surface, then contact resistance increases, but adding more contacts increases device complexity
Solution Approach 1:
The silicon nitride pull-back etch creates a larger opening area before top plate deposition, ensuring void-free top plate surfaces. This preliminary action enables reliable electrical contact through single central contacts, eliminating the need for multiple contacts or complex contact structures while maintaining low contact resistance.
4Quantity of substance
If silicon nitride opening area is smaller than silicon opening area, then trench capacitor density is improved, but voids form at the top plate surface
Solution Approach 1:
A silicon nitride pull-back etch step is introduced as a preliminary action before top plate deposition. This step selectively removes silicon nitride to enlarge the opening area, ensuring it matches or exceeds the silicon opening area below. This prevents void formation during subsequent top plate material deposition while maintaining high trench capacitor density through the deep trench structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces or eliminates surface voids in the top plate, enabling reliable electrical contact and enhancing capacitance density, particularly in high-density trench capacitors, supporting higher voltage applications like 12 V and 20 V, while maintaining simplicity and low implementation costs.
Implementation Method 1
performing a wet nitride etch to ensure adequate space for contact landing
Data Source
AI summary
A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.