Trench Depth Optimization for High and Low Voltage MOS Transistors
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Solution Overview
Problem
The existing method of manufacturing semiconductor devices with integrated high and low withstand voltage MOS transistors using trench isolation struggles to optimize the depth of the tapered portion of the shallow trench, leading to unsatisfactory characteristics for both types of transistors, as it is difficult to ensure both sufficient gate withstanding voltage for high voltage transistors and prevent sub-channel formation in low voltage transistors.
Innovation Solution
A method involving the formation of a first trench with a deeper tapered portion for high withstand voltage MOS transistors and a second trench with a shallower tapered portion for low withstand voltage MOS transistors, where the depth of the tapered portion is optimized to ensure adequate gate oxide film thickness and prevent sub-channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single trench depth is used for both high withstand voltage and low withstand voltage MOS transistors, then the manufacturing process is simplified, but the characteristics of both transistor types become unsatisfactory
Solution Approach 1:
The trench formation process is segmented into two distinct operations: first forming a shallow trench with a tapered portion at a controlled depth, then selectively deepening the trench in the high withstand voltage region. This segmentation allows each region to have optimized trench depth while maintaining process control through separate etching steps with different conditions
Solution Approach 2:
The patent applies local quality by creating different trench depths in different regions: the low withstand voltage region maintains a shallower trench with a tapered portion, while the high withstand voltage region receives an additional deepening step. This local differentiation ensures each transistor type has the optimal trench characteristics for its specific electrical requirements
2Strength
If the tapered portion depth is increased to ensure sufficient gate oxide film thickness for high withstand voltage transistors, then gate withstanding voltage is improved, but sub-channel formation occurs in low withstand voltage transistors
Solution Approach 1:
The etching process is segmented into a first etching step that forms the tapered portion at a depth suitable for low withstand voltage transistors, and a second selective etching step that deepens only the high withstand voltage region trenches. This prevents the tapered portion from being too deep for low voltage devices while still providing sufficient depth for high voltage devices
Solution Approach 2:
Different trench depth characteristics are applied locally: the low withstand voltage region retains a shallower tapered portion that prevents sub-channel formation, while the high withstand voltage region has a deeper trench structure that ensures adequate gate oxide film thickness and withstanding voltage
3Object-generated harmful factors
If the tapered portion depth is decreased to prevent sub-channel formation in low withstand voltage transistors, then sub-channel formation is suppressed, but gate oxide film thickness becomes insufficient for high withstand voltage transistors
Solution Approach 1:
The trench formation is segmented into two stages: the first stage creates a shallow tapered portion that prevents sub-channel formation in low voltage regions, and the second stage selectively deepens trenches in high voltage regions through additional etching steps with modified parameters, ensuring sufficient depth for adequate gate oxide film thickness
4Ease of manufacture
If a single etching condition is used for all trenches, then the manufacturing process is simplified, but optimal trench depth cannot be achieved for both high and low withstand voltage regions
Solution Approach 1:
The etching process is segmented into multiple steps with different conditions: a first etching step using one set of parameters to form the initial tapered portion, and a second selective etching step using different parameters to deepen only the high withstand voltage regions. This segmented approach maintains manufacturing simplicity while achieving precise depth control for each region
Solution Approach 2:
The first etching step performs a preliminary action by forming the tapered portion at a controlled shallow depth that serves as a foundation for both regions. This preliminary structure prevents sub-channel formation in low voltage areas while providing a base from which the high voltage regions can be selectively deepened in a subsequent step
Data Source
AI summary
A high withstand voltage transistor is formed in a high withstand voltage region, and a low withstand voltage transistor is formed in a low withstand voltage region in a method of manufacturing a semiconductor device. The method includes forming a thermal oxide film and a silicon nitride film over the surface of a silicon substrate; forming an opening to the thermal oxide film and the silicon nitride film in each of the high withstand voltage region and the low withstand voltage region; etching the silicon substrate to form trenches; burying a buried oxide film in each of the trenches; removing the thermal oxide film and the silicon nitride film; and forming a thick gate oxide film and a thin oxide film. The depth of a tapered portion of the trench in the low withstand voltage region is shallower than that in the high withstand voltage region.