Trench Semiconductor Edge Termination Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing trench power devices face challenges with edge termination structures, including surface roughness, latent damage, increased manufacturing costs, and parasitic device leakage due to distinct masking and implantation processes used for P-edge regions, which can lead to gate-to-source leakage and source-to-source leakage.
Innovation Solution
The implementation of edge termination structures formed within trenches in semiconductor devices, where edge electrodes are integrally connected with gate electrodes, allowing for simultaneous fabrication using the same steps and voltage application, reducing the need for additional masking and implantation processes, and minimizing surface damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distinct masking and implantation processes are used to form P-edge regions, then edge termination structures are created to avoid breakdown, but surface roughness and latent damage occur leading to increased gate-to-source leakage
Solution Approach 1:
The patent merges the formation of P-edge regions and P-body regions into a single implantation step by using a unified mask pattern. The mask is designed with openings that simultaneously define both the edge termination regions and the body regions, allowing both dopant regions to be formed in one process rather than requiring separate masking and implantation steps. This eliminates the surface roughness and latent damage caused by multiple processing steps.
2Reliability
If distinct masking and implantation steps are used for P-edge regions, then edge termination is achieved, but manufacturing cost increases by 10 to 15 percent
Solution Approach 1:
The patent combines multiple fabrication steps into a single implantation process. By designing a unified mask that patterns both the P-edge termination regions and P-body regions simultaneously, the patent eliminates the need for separate masking and implantation steps. This consolidation reduces manufacturing complexity and cost while maintaining the necessary edge termination functionality.
3Reliability
If P-edge regions are formed using conventional masking and implant processes, then breakdown in edge region is prevented, but parasitic device formation and source-to-source leakage occur
Solution Approach 1:
The patent merges the formation of P-edge and P-body regions into a single simultaneous implantation step. The unified mask pattern ensures proper spacing and alignment between edge termination regions and body regions, preventing the formation of parasitic devices that could cause source-to-source leakage. This approach maintains breakdown prevention while eliminating the harmful leakage effects.
4Reliability
If multiple masking and implantation steps are used, then P-edge regions are formed, but the process time and complexity increase
Solution Approach 1:
The patent merges multiple sequential implantation steps into a single simultaneous implantation process. By using a unified mask that defines both P-edge and P-body regions, the patent reduces the fabrication process time while maintaining proper doping profiles and spacing for edge region protection.
Data Source
AI summary
Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.