Trench-Filled Sidewall Spacers for Uniform Stacked Channel Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is forming inner spacers around all channels without gaps as minimum feature sizes reduce, making it difficult to achieve uniform protection and isolation in multi-channel transistors.
Innovation Solution
A method is developed to form sidewall spacers by filling trenches between hybrid fins and semiconductor fins, using a combination of deposition and etching processes to create uniform fin and gate sidewall spacer portions, ensuring consistent coverage and isolation for vertically stacked channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional recessing and dielectric deposition is used to form inner spacers, then the process is simpler, but gaps form between spacers and channels as minimum feature size reduces
Solution Approach 1:
The method performs preliminary actions by forming cladding layers on fin structures before creating trenches, and by using sacrificial gate structures that are removed later. This preliminary preparation enables subsequent trench formation and spacer deposition to proceed with uniform coverage, eliminating gaps that would otherwise form between spacers and channels at reduced feature sizes.
Solution Approach 2:
The patent introduces an intermediary approach by forming trenches between fin structures and hybrid fins, then depositing dielectric material to create sidewall spacers. This intermediary trench formation process serves as a mediator that enables precise spacer placement and uniform thickness control, resolving the gap-free coverage issue while maintaining manufacturing feasibility.
2Productivity
If minimum feature size is reduced to increase integration density, then more components fit in given area, but forming inner spacers around all channels without gaps becomes challenging
Solution Approach 1:
The patent transitions from a planar spacer formation approach to a three-dimensional approach by forming trenches between vertically stacked fin structures and hybrid fins. This dimensional change enables spacer material to be deposited conformally on all channel surfaces, ensuring uniform coverage and gap-free isolation even as minimum feature sizes reduce and integration density increases.
Solution Approach 2:
The method employs a nested structure where cladding layers are formed on fin structures, followed by trench formation that nests within the overall device architecture. The sidewall spacers are then deposited within these trenches, creating a nested arrangement that ensures precise spacer placement around all channels without gaps, maintaining manufacturing precision at reduced feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform protection and improved isolation between channel layers, reducing leakage and enhancing the performance of multi-channel transistors by maintaining consistent spacer thickness and gap-free coverage.
Implementation Method 1
depositing a dielectric material in place of the recessed semiconductor materials
Implementation Method 2
forming trenches between the fin structures and the hybrid fins by removing the cladding layer
Data Source
AI summary
Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.