Trench Gate DRAM Channel Length Control
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Solution Overview
Problem
Conventional deep trench DRAMs face limitations in channel length due to lithography etching processes, leading to integrity issues and increased field junction leakage current, which degrades device reliability as device sizes shrink.
Innovation Solution
The DRAM design incorporates a substrate with deep trenches and a gate structure that fills into the trench, allowing the channel region to be defined by trench depth, enabling precise control of channel length and width, thus avoiding limitations imposed by lithography etching and enhancing device integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel region length is shortened to improve device integration, then device density increases, but threshold voltage difference and short channel effect occur leading to degraded device reliability
Solution Approach 1:
The patent transitions from planar channel configuration to a three-dimensional structure where the gate electrode is disposed in a trench formed in the substrate. This vertical dimension allows independent control of channel length through trench depth while maintaining shorter effective channel lengths for higher integration, thereby resolving the contradiction between device integration and reliability.
2Ease of manufacture
If lithography etching process is used to define channel length, then manufacturing process is simplified, but channel length cannot be shortened further due to process limitations
Solution Approach 1:
The patent uses trench depth in the vertical dimension to define channel length instead of relying solely on lateral lithography etching. This allows channel length to be controlled by etching depth which can achieve finer precision and shorter lengths, overcoming the limitations of planar lithography while maintaining manufacturing feasibility.
3Productivity
If device size is reduced to increase memory capacity, then memory density improves, but field junction leakage current increases degrading device reliability
Solution Approach 1:
By moving the channel definition to the vertical dimension through trench depth control, the patent enables smaller lateral device footprints for higher density while the vertical gate structure provides better electrostatic control that suppresses field junction leakage current, thus resolving the contradiction between memory density and leakage current.
Data Source
AI summary
A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capacitors includes a lower electrode, an upper electrode, and a capacitor dielectric layer. A device isolation layer is formed in the first mask layer and the substrate for defining an active region. The first mask layer is removed for exposing the substrate, and a semiconductor layer is formed on the exposed substrate. The semiconductor layer and the substrate are patterned for forming trenches, and the bottom of the trench is adjacent to the upper electrodes of the trench capacitor. Gate structures filling into the trenches are formed on the substrate. A doped region is formed in the substrate adjacent to a side of the gate structure.