Trench-Gate Enhancement HEMT Structure for Current Collapse Suppression
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Solution Overview
Problem
Current enhancement mode high electron mobility transistors (HEMTs) based on AlGaN/GaN heterojunctions face significant current collapse effects and dynamic resistance degradation due to hot electron capture, which hampers gate control ability and reliability, especially at high voltage and current operations.
Innovation Solution
The enhancement mode switching device incorporates a trench in the gate region with a p-type semiconductor layer in contact with the channel layer, forming a PN junction that suppresses current collapse and improves gate control by creating a space depletion region, along with varying doping concentrations and periodic composition changes in the p-type semiconductor layer, and includes an n-type semiconductor layer covering the trench for enhanced electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the distance between the P-type gate and the two-dimensional electron gas is reduced to enhance gate control ability, then the gate control ability is improved, but the current collapse effect and dynamic resistance characteristic degradation become more serious due to hot electron capture
Solution Approach 1:
The gate structure is segmented into a P-type gate layer and an N-type semiconductor layer formed in a trench. This segmentation creates a PN junction that divides the gate control mechanism into two functional parts: the P-type gate for electrostatic control and the N-type layer for suppressing hot electron capture, thereby resolving the contradiction between control ability and reliability
Solution Approach 2:
The N-type semiconductor layer acts as an intermediary between the P-type gate and the two-dimensional electron gas. It mediates the interaction by providing a low-resistance path that prevents hot electrons from being captured by the gate, thus improving reliability while maintaining gate control through the PN junction
2Adaptability or versatility
If a P-type gate is used to realize enhancement mode HEMT, then the enhancement mode operation is achieved, but the current collapse effect becomes significant at high voltage and high current operations
Solution Approach 1:
The invention changes the electrical parameters of the gate structure by introducing an N-type semiconductor layer with high electron concentration. This parameter change creates a PN junction that modifies the electric field distribution, preventing the formation of high-field regions that cause hot electron capture and current collapse, while maintaining enhancement mode operation
3Ease of operation
If the trench penetrates through the barrier layer and channel layer to place the p-type semiconductor layer closer to the channel, then the gate control ability is improved, but the device complexity increases
Solution Approach 1:
The N-type semiconductor layer is positioned in the vertical dimension within the trench, creating a three-dimensional PN junction structure. This dimensional arrangement improves gate control by placing the N-type layer close to the channel while keeping the overall structure organized and manufacturable through standard semiconductor fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively cuts off the channel under zero gate bias, enhances gate reliability, and improves resistance to avalanche, short circuits, and surges, while maintaining better dynamic characteristics and reliability.
Implementation Method 1
forming a PN junction that suppresses current collapse and improves gate control by creating a space depletion region
Implementation Method 2
creating a space depletion region
Implementation Method 3
includes an n-type semiconductor layer covering the trench for enhanced electron mobility
Data Source
AI summary
The present disclosure provides enhancement mode switching devices and manufacturing methods thereof. The enhancement mode switching device includes a substrate; a channel structure including a channel layer and a barrier layer. The channel layer is provided on the substrate, and the barrier layer is provided on a side of the channel layer far away from the substrate. A side of the channel structure far away from the substrate is provided with a trench in a gate region, and the trench penetrates through the barrier layer and a part of the channel layer. The enhancement mode switching device includes a p-type semiconductor layer in the gate region, a gate electrode on a side of the p-type semiconductor layer far away from the substrate, a source electrode in the source region, and a drain electrode in the drain region. At least part of the p-type semiconductor layer is in the trench.