Trench Gate MOS Device Current Path Management
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Solution Overview
Problem
Vertical and trench type IGBTs face challenges with low turning-off capability due to uneven current paths and high current density, leading to avalanche breakdown and increased on-voltage, which complicates the realization of high breakdown voltage and high current density requirements.
Innovation Solution
The design incorporates a semiconductor substrate with a base region and emitter region, featuring straight-line-like trenches with a gate electrode and insulator film, where the base region is divided into regions with varying impurity concentrations and resistance connections to manage current flow and reduce on-resistance, while maintaining high breakdown voltage and current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a trench gate structure is used to increase channel density and reduce on-resistance, then current capacity and power loss characteristics improve, but turning-off capability deteriorates due to uneven current paths and high current density
Solution Approach 1:
The patent applies local quality by creating inter-trench surface regions with different impurity concentrations (first and second conductivity type regions) between adjacent trenches. These regions have locally differentiated electrical properties that guide current flow paths, preventing uneven current distribution during turn-off while maintaining the low on-resistance benefits of the trench gate structure.
Solution Approach 2:
The patent segments the inter-trench surface regions into alternating first conductivity type regions and second conductivity type regions. This segmentation creates distinct current paths that distribute current more evenly during turn-off, addressing the turning-off capability issue while preserving the high current density characteristics enabled by the trench gate structure.
2Quantity of substance
If high current density is achieved through trench gate structure, then current capacity improves, but avalanche breakdown risk increases leading to reduced breakdown voltage
Solution Approach 1:
The patent uses local quality by forming inter-trench surface regions with specifically controlled impurity concentrations between the trenches. These regions create localized electrical fields that distribute voltage stress more uniformly during avalanche conditions, preventing premature breakdown while maintaining high current density capability through the trench gate structure.
Data Source
AI summary
A vertical and trench type insulated gate MOS semiconductor device includes a plurality of regions each being provided between adjacent ones of a plurality of the straight-line-like trenches arranged in parallel and forming a surface pattern of a plurality of straight lines. A plurality of first inter-trench surface regions are provided, each with an n+-type emitter region and a p+-type body region formed thereon, and the surfaces of regions are alternately arranged along the trench in the longitudinal direction thereof with an emitter electrode being in common contact with both of the surfaces of the n+-type emitter region and the p+-type body region. A plurality of second inter-trench surface regions are provided each of which is formed along the trench in the longitudinal direction thereof with one of the surface of the p base region and the surface of the n-type semiconductor substrate.